Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18275993 [patent_doc_number] => 11614937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-28 [patent_title] => Accelerator circuit for mathematical operations with immediate values table [patent_app_type] => utility [patent_app_number] => 17/566193 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566193
Accelerator circuit for mathematical operations with immediate values table Dec 29, 2021 Issued
Array ( [id] => 17736614 [patent_doc_number] => 20220222073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => PROCESSOR COMPRISING A DOUBLE MULTIPLICATION AND DOUBLE ADDITION OPERATOR ACTUABLE BY AN INSTRUCTION WITH THREE OPERAND REFERENCES [patent_app_type] => utility [patent_app_number] => 17/565120 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565120
Processor comprising a double multiplication and double addition operator actuable by an instruction with three operand references Dec 28, 2021 Issued
Array ( [id] => 18527648 [patent_doc_number] => 11714639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Data processing device [patent_app_type] => utility [patent_app_number] => 17/565018 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8056 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565018
Data processing device Dec 28, 2021 Issued
Array ( [id] => 18471237 [patent_doc_number] => 20230205523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => HARDWARE DEVICE FOR ENFORCING ATOMICITY FOR MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/562853 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562853
Hardware device for enforcing atomicity for memory operations Dec 26, 2021 Issued
Array ( [id] => 20242778 [patent_doc_number] => 12423096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Methods and devices for signal processing [patent_app_type] => utility [patent_app_number] => 17/560298 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 15507 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560298 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560298
Methods and devices for signal processing Dec 22, 2021 Issued
Array ( [id] => 18471444 [patent_doc_number] => 20230205730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/560637 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560637
Hybrid hardware accelerator and programmable array architecture Dec 22, 2021 Issued
Array ( [id] => 20242778 [patent_doc_number] => 12423096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Methods and devices for signal processing [patent_app_type] => utility [patent_app_number] => 17/560298 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 15507 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560298 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560298
Methods and devices for signal processing Dec 22, 2021 Issued
Array ( [id] => 18561707 [patent_doc_number] => 11726951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Packet transmission method and apparatus [patent_app_type] => utility [patent_app_number] => 17/556322 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556322
Packet transmission method and apparatus Dec 19, 2021 Issued
Array ( [id] => 18038332 [patent_doc_number] => 20220382548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => COMPILER, COMPILATION METHOD, AND COMPILER DEVICE [patent_app_type] => utility [patent_app_number] => 17/552358 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552358
Non-transitory computer-readable recording medium, compilation method, and compiler device Dec 15, 2021 Issued
Array ( [id] => 19451025 [patent_doc_number] => 20240311155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => Processor and Method for Executing an Instruction with a Processor [patent_app_type] => utility [patent_app_number] => 18/279664 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18279664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/279664
Processor and method for executing an instruction with a processor Dec 8, 2021 Issued
Array ( [id] => 20331614 [patent_doc_number] => 12461891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Neural network accelerator [patent_app_type] => utility [patent_app_number] => 18/573964 [patent_app_country] => US [patent_app_date] => 2021-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 50 [patent_no_of_words] => 9047 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18573964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/573964
Neural network accelerator Nov 24, 2021 Issued
Array ( [id] => 18330930 [patent_doc_number] => 11636174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs [patent_app_type] => utility [patent_app_number] => 17/527882 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 29794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527882
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs Nov 15, 2021 Issued
Array ( [id] => 18275991 [patent_doc_number] => 11614935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Calculation engine for performing calculations based on dependencies in a self-describing data system [patent_app_type] => utility [patent_app_number] => 17/526511 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526511
Calculation engine for performing calculations based on dependencies in a self-describing data system Nov 14, 2021 Issued
Array ( [id] => 18519903 [patent_doc_number] => 11709795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Electronic device including main processor and systolic array processor and operating method of electronic device [patent_app_type] => utility [patent_app_number] => 17/525146 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6521 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525146 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525146
Electronic device including main processor and systolic array processor and operating method of electronic device Nov 11, 2021 Issued
Array ( [id] => 18592006 [patent_doc_number] => 11740904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Vector friendly instruction format and execution thereof [patent_app_type] => utility [patent_app_number] => 17/524624 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 78 [patent_no_of_words] => 31719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524624 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524624
Vector friendly instruction format and execution thereof Nov 10, 2021 Issued
Array ( [id] => 18351694 [patent_doc_number] => 20230139805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => CONTROL UNIT FOR QUBITS [patent_app_type] => utility [patent_app_number] => 17/453499 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453499
Control unit for qubits Nov 3, 2021 Issued
Array ( [id] => 17430449 [patent_doc_number] => 20220058158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING MACHINES USING SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 17/518202 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518202
Computing efficient cross channel operations in parallel computing machines using systolic arrays Nov 2, 2021 Issued
Array ( [id] => 18519902 [patent_doc_number] => 11709794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Exchange between stacked die [patent_app_type] => utility [patent_app_number] => 17/451372 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14721 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451372
Exchange between stacked die Oct 18, 2021 Issued
Array ( [id] => 17674951 [patent_doc_number] => 20220188118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => ARITHMETIC PROCESSING CIRCUIT AND ARITHMETIC PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/449957 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/449957
Arithmetic processing circuit and arithmetic processing method Oct 4, 2021 Issued
Array ( [id] => 18119190 [patent_doc_number] => 11550584 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-10 [patent_title] => Implementing specialized instructions for accelerating Smith-Waterman sequence alignments [patent_app_type] => utility [patent_app_number] => 17/491279 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 30005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491279
Implementing specialized instructions for accelerating Smith-Waterman sequence alignments Sep 29, 2021 Issued
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