Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
08/317886 DIGITAL SIGNAL PROCESSOR HAVING LINK PORTS FOR POINT-TO-POINT COMMUNICATION Oct 3, 1994 Abandoned
08/317891 BUS ARCHITECTURE FOR DIGITAL SIGNAL PROCESSOR ALLOWING TIME MULTIPLEXED ACCESS TO MEMORY BANKS Oct 3, 1994 Abandoned
Array ( [id] => 3662976 [patent_doc_number] => 05685005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Digital signal processor configured for multiprocessing' [patent_app_type] => 1 [patent_app_number] => 8/317744 [patent_app_country] => US [patent_app_date] => 1994-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12126 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/685/05685005.pdf [firstpage_image] =>[orig_patent_app_number] => 317744 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317744
Digital signal processor configured for multiprocessing Oct 3, 1994 Issued
Array ( [id] => 3526853 [patent_doc_number] => 05513366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Method and system for dynamically reconfiguring a register file in a vector processor' [patent_app_type] => 1 [patent_app_number] => 8/313971 [patent_app_country] => US [patent_app_date] => 1994-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7886 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513366.pdf [firstpage_image] =>[orig_patent_app_number] => 313971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/313971
Method and system for dynamically reconfiguring a register file in a vector processor Sep 27, 1994 Issued
Array ( [id] => 3564763 [patent_doc_number] => 05493678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Method in a structure editor' [patent_app_type] => 1 [patent_app_number] => 8/313661 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 20090 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493678.pdf [firstpage_image] =>[orig_patent_app_number] => 313661 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/313661
Method in a structure editor Sep 26, 1994 Issued
Array ( [id] => 3569251 [patent_doc_number] => 05502835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Method for synchronously accessing memory' [patent_app_type] => 1 [patent_app_number] => 8/298885 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 16691 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502835.pdf [firstpage_image] =>[orig_patent_app_number] => 298885 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/298885
Method for synchronously accessing memory Aug 30, 1994 Issued
Array ( [id] => 3506164 [patent_doc_number] => 05537602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Process system for controlling bus system to communicate data between resource and processor' [patent_app_type] => 1 [patent_app_number] => 8/288356 [patent_app_country] => US [patent_app_date] => 1994-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17553 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537602.pdf [firstpage_image] =>[orig_patent_app_number] => 288356 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/288356
Process system for controlling bus system to communicate data between resource and processor Aug 9, 1994 Issued
Array ( [id] => 3553500 [patent_doc_number] => 05481747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Synchronous method and apparatus for processors' [patent_app_type] => 1 [patent_app_number] => 8/281990 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9232 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481747.pdf [firstpage_image] =>[orig_patent_app_number] => 281990 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/281990
Synchronous method and apparatus for processors Jul 28, 1994 Issued
Array ( [id] => 3529853 [patent_doc_number] => 05506982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices' [patent_app_type] => 1 [patent_app_number] => 8/278245 [patent_app_country] => US [patent_app_date] => 1994-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 53 [patent_no_of_words] => 14711 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506982.pdf [firstpage_image] =>[orig_patent_app_number] => 278245 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/278245
Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices Jul 20, 1994 Issued
Array ( [id] => 3497369 [patent_doc_number] => 05426746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Microcontroller with program recomposing function' [patent_app_type] => 1 [patent_app_number] => 8/272863 [patent_app_country] => US [patent_app_date] => 1994-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2485 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426746.pdf [firstpage_image] =>[orig_patent_app_number] => 272863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/272863
Microcontroller with program recomposing function Jul 7, 1994 Issued
08/269238 MEMORY BANK ADDRESSING SCHEME Jun 29, 1994 Abandoned
Array ( [id] => 3671016 [patent_doc_number] => 05659781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Bidirectional systolic ring network' [patent_app_type] => 1 [patent_app_number] => 8/269341 [patent_app_country] => US [patent_app_date] => 1994-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 69 [patent_no_of_words] => 33728 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 458 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659781.pdf [firstpage_image] =>[orig_patent_app_number] => 269341 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/269341
Bidirectional systolic ring network Jun 28, 1994 Issued
Array ( [id] => 3601118 [patent_doc_number] => 05517617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Automatic assignment of addresses in a computer communications network' [patent_app_type] => 1 [patent_app_number] => 8/268214 [patent_app_country] => US [patent_app_date] => 1994-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 8213 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517617.pdf [firstpage_image] =>[orig_patent_app_number] => 268214 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/268214
Automatic assignment of addresses in a computer communications network Jun 28, 1994 Issued
08/268222 VIRTUAL ADDRESS CACHE PROTECTION BITS HANDLING METHOD AND APPARATUS Jun 28, 1994 Abandoned
Array ( [id] => 3526373 [patent_doc_number] => 05513334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Memory device with switching of data stream modes' [patent_app_type] => 1 [patent_app_number] => 8/266948 [patent_app_country] => US [patent_app_date] => 1994-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4652 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513334.pdf [firstpage_image] =>[orig_patent_app_number] => 266948 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/266948
Memory device with switching of data stream modes Jun 26, 1994 Issued
Array ( [id] => 3625514 [patent_doc_number] => 05566311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Semiconductor memory controller for reducing pass through current' [patent_app_type] => 1 [patent_app_number] => 8/264712 [patent_app_country] => US [patent_app_date] => 1994-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 9326 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566311.pdf [firstpage_image] =>[orig_patent_app_number] => 264712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/264712
Semiconductor memory controller for reducing pass through current Jun 22, 1994 Issued
Array ( [id] => 3744137 [patent_doc_number] => 05636359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Performance enhancement system and method for a hierarchical data cache using a RAID parity scheme' [patent_app_type] => 1 [patent_app_number] => 8/262208 [patent_app_country] => US [patent_app_date] => 1994-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 17798 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636359.pdf [firstpage_image] =>[orig_patent_app_number] => 262208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/262208
Performance enhancement system and method for a hierarchical data cache using a RAID parity scheme Jun 19, 1994 Issued
Array ( [id] => 3547735 [patent_doc_number] => 05557769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Mechanism and protocol for maintaining cache coherency within an integrated processor' [patent_app_type] => 1 [patent_app_number] => 8/261242 [patent_app_country] => US [patent_app_date] => 1994-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5554 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557769.pdf [firstpage_image] =>[orig_patent_app_number] => 261242 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/261242
Mechanism and protocol for maintaining cache coherency within an integrated processor Jun 16, 1994 Issued
Array ( [id] => 3556978 [patent_doc_number] => 05555433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Circuit for interfacing data busses' [patent_app_type] => 1 [patent_app_number] => 8/259403 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2907 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555433.pdf [firstpage_image] =>[orig_patent_app_number] => 259403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/259403
Circuit for interfacing data busses Jun 12, 1994 Issued
Array ( [id] => 3494978 [patent_doc_number] => 05446851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Instruction supplier for a microprocessor capable of preventing a functional error operation' [patent_app_type] => 1 [patent_app_number] => 8/257454 [patent_app_country] => US [patent_app_date] => 1994-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10870 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446851.pdf [firstpage_image] =>[orig_patent_app_number] => 257454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/257454
Instruction supplier for a microprocessor capable of preventing a functional error operation Jun 7, 1994 Issued
Menu