| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3596445
[patent_doc_number] => 05581773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements'
[patent_app_type] => 1
[patent_app_number] => 7/881616
[patent_app_country] => US
[patent_app_date] => 1992-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 5232
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581773.pdf
[firstpage_image] =>[orig_patent_app_number] => 881616
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/881616 | Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements | May 11, 1992 | Issued |
| 07/879007 | DATA PROTECTIVE MICROPROCESSOR CIRCUIT FOR PORTABLE DATA CARRIERS, FOR EXAMPLE CREDIT CARDS | May 5, 1992 | Abandoned |
Array
(
[id] => 3041916
[patent_doc_number] => 05349685
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-20
[patent_title] => 'Multipurpose bus interface utilizing a digital signal processor'
[patent_app_type] => 1
[patent_app_number] => 7/878713
[patent_app_country] => US
[patent_app_date] => 1992-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 59
[patent_no_of_words] => 36896
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 722
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/349/05349685.pdf
[firstpage_image] =>[orig_patent_app_number] => 878713
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/878713 | Multipurpose bus interface utilizing a digital signal processor | May 4, 1992 | Issued |
Array
(
[id] => 3456917
[patent_doc_number] => 05388249
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-07
[patent_title] => 'Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices'
[patent_app_type] => 1
[patent_app_number] => 7/872174
[patent_app_country] => US
[patent_app_date] => 1992-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 53
[patent_no_of_words] => 14707
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/388/05388249.pdf
[firstpage_image] =>[orig_patent_app_number] => 872174
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/872174 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Apr 21, 1992 | Issued |
Array
(
[id] => 3604393
[patent_doc_number] => 05586337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'Programmable controller with timing control'
[patent_app_type] => 1
[patent_app_number] => 7/869508
[patent_app_country] => US
[patent_app_date] => 1992-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 1921
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/586/05586337.pdf
[firstpage_image] =>[orig_patent_app_number] => 869508
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/869508 | Programmable controller with timing control | Apr 15, 1992 | Issued |
Array
(
[id] => 3128960
[patent_doc_number] => 05410677
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-25
[patent_title] => 'Apparatus for translating data formats starting at an arbitrary byte position'
[patent_app_type] => 1
[patent_app_number] => 7/815828
[patent_app_country] => US
[patent_app_date] => 1991-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9671
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/410/05410677.pdf
[firstpage_image] =>[orig_patent_app_number] => 815828
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/815828 | Apparatus for translating data formats starting at an arbitrary byte position | Dec 29, 1991 | Issued |
| 07/815566 | MICROCODE ENTRY TABLE SIZE REDUCTION APPARATUS AND METHOD | Dec 25, 1991 | Abandoned |
Array
(
[id] => 3428160
[patent_doc_number] => 05394541
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-28
[patent_title] => 'Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals'
[patent_app_type] => 1
[patent_app_number] => 7/811825
[patent_app_country] => US
[patent_app_date] => 1991-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 6168
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/394/05394541.pdf
[firstpage_image] =>[orig_patent_app_number] => 811825
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/811825 | Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals | Dec 19, 1991 | Issued |
Array
(
[id] => 3540250
[patent_doc_number] => 05542068
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Method and system for storing floating point numbers to reduce storage space'
[patent_app_type] => 1
[patent_app_number] => 7/804425
[patent_app_country] => US
[patent_app_date] => 1991-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2415
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/542/05542068.pdf
[firstpage_image] =>[orig_patent_app_number] => 804425
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/804425 | Method and system for storing floating point numbers to reduce storage space | Dec 9, 1991 | Issued |
| 07/803670 | SEQUENTIAL EEPROM WRITING APPARATUS | Dec 2, 1991 | Abandoned |
| 07/793740 | A PERFORMANCE AND MEASUREMENT SYSTEM WHICH LOGS DATA PERTAINING TO GROUPS OF PROCESSES | Nov 17, 1991 | Abandoned |
| 07/788229 | SINGLE-CHIP MICRO-COMPUTER HAVING A PLURALITY OF OPERATION MODES | Nov 4, 1991 | Abandoned |
Array
(
[id] => 3041300
[patent_doc_number] => 05349653
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-20
[patent_title] => 'Apparatus for converting parallel bits of an electrical data signal into serial bits of an optical data signal utilizing an optical time delay'
[patent_app_type] => 1
[patent_app_number] => 7/775030
[patent_app_country] => US
[patent_app_date] => 1991-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 5630
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/349/05349653.pdf
[firstpage_image] =>[orig_patent_app_number] => 775030
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/775030 | Apparatus for converting parallel bits of an electrical data signal into serial bits of an optical data signal utilizing an optical time delay | Oct 10, 1991 | Issued |
| 90/002471 | DATA PROCESSING SYSTEM HAVING A DATA COHERENCE SOLUTION | Oct 7, 1991 | Issued |
Array
(
[id] => 3008245
[patent_doc_number] => 05367696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-22
[patent_title] => 'Register allocation technique in a program translating apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/769446
[patent_app_country] => US
[patent_app_date] => 1991-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 5507
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/367/05367696.pdf
[firstpage_image] =>[orig_patent_app_number] => 769446
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/769446 | Register allocation technique in a program translating apparatus | Sep 30, 1991 | Issued |
Array
(
[id] => 3460327
[patent_doc_number] => 05386537
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'System with reduced instruction set processor accessing plural memories at different speeds using bank interleaving'
[patent_app_type] => 1
[patent_app_number] => 7/766524
[patent_app_country] => US
[patent_app_date] => 1991-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3929
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/386/05386537.pdf
[firstpage_image] =>[orig_patent_app_number] => 766524
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/766524 | System with reduced instruction set processor accessing plural memories at different speeds using bank interleaving | Sep 26, 1991 | Issued |
Array
(
[id] => 3084933
[patent_doc_number] => 05337412
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-09
[patent_title] => 'Method and apparatus for substituting real and virtual devices independent from an data processing system application program'
[patent_app_type] => 1
[patent_app_number] => 7/765849
[patent_app_country] => US
[patent_app_date] => 1991-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5233
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/337/05337412.pdf
[firstpage_image] =>[orig_patent_app_number] => 765849
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/765849 | Method and apparatus for substituting real and virtual devices independent from an data processing system application program | Sep 25, 1991 | Issued |
Array
(
[id] => 3067191
[patent_doc_number] => 05345568
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-06
[patent_title] => 'Instruction fetch circuit which allows for independent decoding and execution of instructions'
[patent_app_type] => 1
[patent_app_number] => 7/762629
[patent_app_country] => US
[patent_app_date] => 1991-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1973
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/345/05345568.pdf
[firstpage_image] =>[orig_patent_app_number] => 762629
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/762629 | Instruction fetch circuit which allows for independent decoding and execution of instructions | Sep 18, 1991 | Issued |
| 07/760426 | APPARATUS AND METHOD FOR BURST DATA TRANSFER EMPLOYING A PAUSE AT FIXED DATA INTERVALS | Sep 15, 1991 | Abandoned |
Array
(
[id] => 3082687
[patent_doc_number] => 05361369
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-01
[patent_title] => 'Synchronous method of, and apparatus for, allowing a processor to process a next task before synchronization between a predetermined group of processors'
[patent_app_type] => 1
[patent_app_number] => 7/759529
[patent_app_country] => US
[patent_app_date] => 1991-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 9230
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/361/05361369.pdf
[firstpage_image] =>[orig_patent_app_number] => 759529
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/759529 | Synchronous method of, and apparatus for, allowing a processor to process a next task before synchronization between a predetermined group of processors | Sep 12, 1991 | Issued |