Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3128881 [patent_doc_number] => 05410673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Method and apparatus for simulating a logic circuit having a plurality of interconnect logic blocks' [patent_app_type] => 1 [patent_app_number] => 7/758050 [patent_app_country] => US [patent_app_date] => 1991-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4607 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410673.pdf [firstpage_image] =>[orig_patent_app_number] => 758050 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/758050
Method and apparatus for simulating a logic circuit having a plurality of interconnect logic blocks Sep 11, 1991 Issued
07/754923 AUTOMATED GENERATION OF FILE ACCESS CONTROL SYSTEM IN A DATA PROCESSING SYSTEM WITH FRONT END PROCESSING OF A MASTER LIST Sep 3, 1991 Abandoned
Array ( [id] => 3127751 [patent_doc_number] => 05396610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Register address specifying circuit for simultaneously accessing two registers' [patent_app_type] => 1 [patent_app_number] => 7/752129 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 36 [patent_no_of_words] => 15205 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396610.pdf [firstpage_image] =>[orig_patent_app_number] => 752129 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/752129
Register address specifying circuit for simultaneously accessing two registers Aug 28, 1991 Issued
Array ( [id] => 3035252 [patent_doc_number] => 05327544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Method and apparatus for designing gateways for computer networks' [patent_app_type] => 1 [patent_app_number] => 7/752127 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 5350 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327544.pdf [firstpage_image] =>[orig_patent_app_number] => 752127 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/752127
Method and apparatus for designing gateways for computer networks Aug 28, 1991 Issued
Array ( [id] => 3041807 [patent_doc_number] => 05349679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Communication control unit for selecting a control mode of data communication and selectively bypassing an interprocessor interface' [patent_app_type] => 1 [patent_app_number] => 7/750827 [patent_app_country] => US [patent_app_date] => 1991-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5332 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349679.pdf [firstpage_image] =>[orig_patent_app_number] => 750827 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/750827
Communication control unit for selecting a control mode of data communication and selectively bypassing an interprocessor interface Aug 26, 1991 Issued
Array ( [id] => 3437592 [patent_doc_number] => 05404461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Broadcast/switching apparatus for executing broadcast/multi-cast transfers over unbuffered asynchronous switching networks' [patent_app_type] => 1 [patent_app_number] => 7/748316 [patent_app_country] => US [patent_app_date] => 1991-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 47 [patent_no_of_words] => 18125 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404461.pdf [firstpage_image] =>[orig_patent_app_number] => 748316 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/748316
Broadcast/switching apparatus for executing broadcast/multi-cast transfers over unbuffered asynchronous switching networks Aug 20, 1991 Issued
07/739840 INSTRUCTION SUPPLIER FOR A MICROPROCESSOR CAPABLE OF PREVENTING A FUNCTIONAL ERROR OPERATION Aug 1, 1991 Abandoned
07/739889 METHOD AND APPARATUS FOR CONFIGURATION OF COMPUTER SYSTEM AND CIRCUIT BOARDS Aug 1, 1991 Abandoned
Array ( [id] => 3467417 [patent_doc_number] => 05452468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Computer system with parallel processing for information organization' [patent_app_type] => 1 [patent_app_number] => 7/738325 [patent_app_country] => US [patent_app_date] => 1991-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6544 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452468.pdf [firstpage_image] =>[orig_patent_app_number] => 738325 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/738325
Computer system with parallel processing for information organization Jul 30, 1991 Issued
Array ( [id] => 3420138 [patent_doc_number] => 05438671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Method and system for transferring compressed bytes of information between separate hard disk drive units' [patent_app_type] => 1 [patent_app_number] => 7/732842 [patent_app_country] => US [patent_app_date] => 1991-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6066 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438671.pdf [firstpage_image] =>[orig_patent_app_number] => 732842 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/732842
Method and system for transferring compressed bytes of information between separate hard disk drive units Jul 18, 1991 Issued
Array ( [id] => 3093695 [patent_doc_number] => 05321820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'Processor for executing a conditional branch instruction at a high speed by pre-reading a result flag' [patent_app_type] => 1 [patent_app_number] => 7/729126 [patent_app_country] => US [patent_app_date] => 1991-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2877 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/321/05321820.pdf [firstpage_image] =>[orig_patent_app_number] => 729126 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/729126
Processor for executing a conditional branch instruction at a high speed by pre-reading a result flag Jul 11, 1991 Issued
Array ( [id] => 3127636 [patent_doc_number] => 05396604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'System and method for reducing the penalty associated with data cache misses' [patent_app_type] => 1 [patent_app_number] => 7/729132 [patent_app_country] => US [patent_app_date] => 1991-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3137 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396604.pdf [firstpage_image] =>[orig_patent_app_number] => 729132 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/729132
System and method for reducing the penalty associated with data cache misses Jul 11, 1991 Issued
Array ( [id] => 3126027 [patent_doc_number] => 05414830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Apparatus for serialization and deserialization of data, and resultant system for digital transmission of serial data' [patent_app_type] => 1 [patent_app_number] => 7/727429 [patent_app_country] => US [patent_app_date] => 1991-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 8435 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414830.pdf [firstpage_image] =>[orig_patent_app_number] => 727429 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/727429
Apparatus for serialization and deserialization of data, and resultant system for digital transmission of serial data Jul 8, 1991 Issued
Array ( [id] => 2904775 [patent_doc_number] => 05210832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Multiple domain emulation system with separate domain facilities which tests for emulated instruction exceptions before completion of operand fetch cycle' [patent_app_type] => 1 [patent_app_number] => 7/725905 [patent_app_country] => US [patent_app_date] => 1991-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10812 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210832.pdf [firstpage_image] =>[orig_patent_app_number] => 725905 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/725905
Multiple domain emulation system with separate domain facilities which tests for emulated instruction exceptions before completion of operand fetch cycle Jul 2, 1991 Issued
Array ( [id] => 3465219 [patent_doc_number] => 05379395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Semiconductor integrated circuit for central processor interfacing which enables random and serial access to single port memories' [patent_app_type] => 1 [patent_app_number] => 7/724668 [patent_app_country] => US [patent_app_date] => 1991-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3857 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379395.pdf [firstpage_image] =>[orig_patent_app_number] => 724668 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/724668
Semiconductor integrated circuit for central processor interfacing which enables random and serial access to single port memories Jul 1, 1991 Issued
Array ( [id] => 2927992 [patent_doc_number] => 05179696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Generator detecting internal and external ready signals for generating a bus cycle end signal for microprocessor debugging operation' [patent_app_type] => 1 [patent_app_number] => 7/718912 [patent_app_country] => US [patent_app_date] => 1991-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2958 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179696.pdf [firstpage_image] =>[orig_patent_app_number] => 718912 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/718912
Generator detecting internal and external ready signals for generating a bus cycle end signal for microprocessor debugging operation Jun 23, 1991 Issued
07/714243 SYMBOLIC-NUMERICAL OBJECTIVE CAE PROGRAMMING METHODOLOGY FOR THE ENHANCEMENT OF ENGINEERING PRODUCTIVITY Jun 11, 1991 Abandoned
Array ( [id] => 3008183 [patent_doc_number] => 05367693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'System for dialog among processors and dispatching processes to processors which monitors the number of acknowledgements to processing requests' [patent_app_type] => 1 [patent_app_number] => 7/710340 [patent_app_country] => US [patent_app_date] => 1991-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8565 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367693.pdf [firstpage_image] =>[orig_patent_app_number] => 710340 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/710340
System for dialog among processors and dispatching processes to processors which monitors the number of acknowledgements to processing requests Jun 4, 1991 Issued
Array ( [id] => 3067286 [patent_doc_number] => 05345574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Memory card having controller providing adjustable refresh to a plurality of DRAMs' [patent_app_type] => 1 [patent_app_number] => 7/708730 [patent_app_country] => US [patent_app_date] => 1991-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3929 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/345/05345574.pdf [firstpage_image] =>[orig_patent_app_number] => 708730 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/708730
Connection state confirmation system and method for expansion unit May 30, 1991 Issued
Array ( [id] => 3067286 [patent_doc_number] => 05345574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Memory card having controller providing adjustable refresh to a plurality of DRAMs' [patent_app_type] => 1 [patent_app_number] => 7/708730 [patent_app_country] => US [patent_app_date] => 1991-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3929 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/345/05345574.pdf [firstpage_image] =>[orig_patent_app_number] => 708730 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/708730
Connection state confirmation system and method for expansion unit May 30, 1991 Issued
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