Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3035061 [patent_doc_number] => 05327534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Detection of duplicate alias addresses' [patent_app_type] => 1 [patent_app_number] => 7/559031 [patent_app_country] => US [patent_app_date] => 1990-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 9370 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327534.pdf [firstpage_image] =>[orig_patent_app_number] => 559031 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/559031
Detection of duplicate alias addresses Jul 29, 1990 Issued
Array ( [id] => 3058365 [patent_doc_number] => 05287463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transitions' [patent_app_type] => 1 [patent_app_number] => 7/562433 [patent_app_country] => US [patent_app_date] => 1990-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6921 [patent_no_of_claims] => 120 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287463.pdf [firstpage_image] =>[orig_patent_app_number] => 562433 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/562433
Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transitions Jul 18, 1990 Issued
Array ( [id] => 3438012 [patent_doc_number] => 05404491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Subscriber module for connection to a plurality of subscriber terminals and to an integrated services digital communication network (ISDN)' [patent_app_type] => 1 [patent_app_number] => 7/553165 [patent_app_country] => US [patent_app_date] => 1990-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1274 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404491.pdf [firstpage_image] =>[orig_patent_app_number] => 553165 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/553165
Subscriber module for connection to a plurality of subscriber terminals and to an integrated services digital communication network (ISDN) Jul 12, 1990 Issued
Array ( [id] => 2977186 [patent_doc_number] => 05265229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Single load, multiple issue queue with error recovery capability' [patent_app_type] => 1 [patent_app_number] => 7/547661 [patent_app_country] => US [patent_app_date] => 1990-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5575 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/265/05265229.pdf [firstpage_image] =>[orig_patent_app_number] => 547661 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/547661
Single load, multiple issue queue with error recovery capability Jul 1, 1990 Issued
Array ( [id] => 3908138 [patent_doc_number] => 05778423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Prefetch instruction for improving performance in reduced instruction set processor' [patent_app_type] => 1 [patent_app_number] => 7/547630 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 15604 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778423.pdf [firstpage_image] =>[orig_patent_app_number] => 547630 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/547630
Prefetch instruction for improving performance in reduced instruction set processor Jun 28, 1990 Issued
07/547804 BRANCH PREDICTION UNIT FOR HIGH-PERFORMANCE PROCESSOR Jun 28, 1990 Abandoned
Array ( [id] => 3015757 [patent_doc_number] => 05371873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Image data processing terminal equipment coupled to an external device allowing independent use of memory area by the external device' [patent_app_type] => 1 [patent_app_number] => 7/542191 [patent_app_country] => US [patent_app_date] => 1990-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5779 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371873.pdf [firstpage_image] =>[orig_patent_app_number] => 542191 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542191
Image data processing terminal equipment coupled to an external device allowing independent use of memory area by the external device Jun 20, 1990 Issued
Array ( [id] => 3093745 [patent_doc_number] => 05321823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'Digital processor with bit mask for counting registers for fast register saves' [patent_app_type] => 1 [patent_app_number] => 7/542636 [patent_app_country] => US [patent_app_date] => 1990-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8987 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/321/05321823.pdf [firstpage_image] =>[orig_patent_app_number] => 542636 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542636
Digital processor with bit mask for counting registers for fast register saves Jun 20, 1990 Issued
07/540378 MICROPROCESSOR SYSTEM HAVING A SINGLE, COMMON INTERNAL BUS TRANSFERRING DATA AND INSTRUCTIONS IN DIFFERENT STATES OF A MACHINE CYCLE Jun 18, 1990 Abandoned
07/540253 BRANCH INSTRUCTION EXECUTING DEVICE FOR TRACING BRANCH INSTRUMENTS BASED ON INSTURCTION TYPE Jun 18, 1990 Abandoned
Array ( [id] => 2949147 [patent_doc_number] => 05247694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'System and method for generating communications arrangements for routing data in a massively parallel processing system' [patent_app_type] => 1 [patent_app_number] => 7/538184 [patent_app_country] => US [patent_app_date] => 1990-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 15838 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247694.pdf [firstpage_image] =>[orig_patent_app_number] => 538184 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/538184
System and method for generating communications arrangements for routing data in a massively parallel processing system Jun 13, 1990 Issued
Array ( [id] => 2992726 [patent_doc_number] => 05253359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Control and maintenance subsystem network for use with a multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 7/535901 [patent_app_country] => US [patent_app_date] => 1990-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5449 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/253/05253359.pdf [firstpage_image] =>[orig_patent_app_number] => 535901 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/535901
Control and maintenance subsystem network for use with a multiprocessor computer system Jun 10, 1990 Issued
07/533257 METHOD FOR AUTOMATIC OPTIMIZATION OF CPU SOFTWARE OF 86-CLASS MICROPROCESSORS IN A NETWORK ENVIRONMENT Jun 3, 1990 Abandoned
Array ( [id] => 2905379 [patent_doc_number] => 05210864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Pipelined microprocessor with instruction execution control unit which receives instructions from separate path in test mode for testing instruction execution pipeline' [patent_app_type] => 1 [patent_app_number] => 7/531482 [patent_app_country] => US [patent_app_date] => 1990-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 52 [patent_no_of_words] => 20277 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210864.pdf [firstpage_image] =>[orig_patent_app_number] => 531482 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/531482
Pipelined microprocessor with instruction execution control unit which receives instructions from separate path in test mode for testing instruction execution pipeline May 30, 1990 Issued
Array ( [id] => 2818367 [patent_doc_number] => 05148540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'System with backup of data storage status and device identification for enabling system recovery after powerloss' [patent_app_type] => 1 [patent_app_number] => 7/489888 [patent_app_country] => US [patent_app_date] => 1990-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3429 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148540.pdf [firstpage_image] =>[orig_patent_app_number] => 489888 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/489888
System with backup of data storage status and device identification for enabling system recovery after powerloss Mar 6, 1990 Issued
Array ( [id] => 2815941 [patent_doc_number] => 05125076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'System for routing messages in a vertex symmetric network by using addresses formed from permutations of the transmission line indicees' [patent_app_type] => 1 [patent_app_number] => 7/488445 [patent_app_country] => US [patent_app_date] => 1990-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6910 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/125/05125076.pdf [firstpage_image] =>[orig_patent_app_number] => 488445 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/488445
System for routing messages in a vertex symmetric network by using addresses formed from permutations of the transmission line indicees Feb 26, 1990 Issued
Array ( [id] => 2816922 [patent_doc_number] => 05146571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Remapping defects in a storage system through the use of a tree structure' [patent_app_type] => 1 [patent_app_number] => 7/488454 [patent_app_country] => US [patent_app_date] => 1990-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 9858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146571.pdf [firstpage_image] =>[orig_patent_app_number] => 488454 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/488454
Remapping defects in a storage system through the use of a tree structure Feb 25, 1990 Issued
Array ( [id] => 2999002 [patent_doc_number] => 05251322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-05 [patent_title] => 'Method of operating a computer graphics system including asynchronously traversing its nodes' [patent_app_type] => 1 [patent_app_number] => 7/477151 [patent_app_country] => US [patent_app_date] => 1990-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 24926 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/251/05251322.pdf [firstpage_image] =>[orig_patent_app_number] => 477151 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/477151
Method of operating a computer graphics system including asynchronously traversing its nodes Feb 7, 1990 Issued
Array ( [id] => 2934340 [patent_doc_number] => 05201057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'System for extracting low level concurrency from serial instruction streams' [patent_app_type] => 1 [patent_app_number] => 7/474247 [patent_app_country] => US [patent_app_date] => 1990-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 34 [patent_no_of_words] => 17246 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/201/05201057.pdf [firstpage_image] =>[orig_patent_app_number] => 474247 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/474247
System for extracting low level concurrency from serial instruction streams Feb 4, 1990 Issued
07/468490 MICROCOMPUTER FOR DIGITAL SIGNAL PROCESSING Jan 22, 1990 Abandoned
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