Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18772767 [patent_doc_number] => 20230367593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => RISC-V-based Artificial Intelligence Inference Method and System [patent_app_type] => utility [patent_app_number] => 18/246662 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/246662
RISC-V-based artificial intelligence inference method and system Sep 29, 2021 Issued
Array ( [id] => 18299615 [patent_doc_number] => 20230109301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => SPARSE SYSTOLIC ARRAY DESIGN [patent_app_type] => utility [patent_app_number] => 17/490830 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/490830
Sparse systolic array design Sep 29, 2021 Issued
Array ( [id] => 18283252 [patent_doc_number] => 20230098724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => COPY A SUBSET OF STATUS FLAGS FROM A CONTROL AND STATUS REGISTER TO A FLAGS REGISTER [patent_app_type] => utility [patent_app_number] => 17/485374 [patent_app_country] => US [patent_app_date] => 2021-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485374
Copy a subset of status flags from a control and status register to a flags register Sep 24, 2021 Issued
Array ( [id] => 18218169 [patent_doc_number] => 11593106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-28 [patent_title] => Circuits and methods for vector sorting in a microprocessor [patent_app_type] => utility [patent_app_number] => 17/448865 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 17731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448865
Circuits and methods for vector sorting in a microprocessor Sep 23, 2021 Issued
Array ( [id] => 17779147 [patent_doc_number] => 20220245497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => Quantum Approximate Optimization [patent_app_type] => utility [patent_app_number] => 17/473304 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473304
Quantum Approximate Optimization Sep 12, 2021 Abandoned
Array ( [id] => 17706800 [patent_doc_number] => 20220206806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => INSTRUCTION SIMULATION DEVICE AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/471167 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471167
Instruction simulation device and method thereof Sep 9, 2021 Issued
Array ( [id] => 18890001 [patent_doc_number] => 11868774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Processor with hardware supported memory buffer overflow detection [patent_app_type] => utility [patent_app_number] => 17/469018 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469018
Processor with hardware supported memory buffer overflow detection Sep 7, 2021 Issued
Array ( [id] => 18222272 [patent_doc_number] => 20230061266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => HIERARCHICAL RING-BASED INTERCONNECTION NETWORK FOR SYMMETRIC MULTIPROCESSORS [patent_app_type] => utility [patent_app_number] => 17/446422 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446422 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446422
Hierarchical ring-based interconnection network for symmetric multiprocessors Aug 29, 2021 Issued
Array ( [id] => 17521957 [patent_doc_number] => 20220107806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS [patent_app_type] => utility [patent_app_number] => 17/461949 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461949 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461949
Rotate instructions that complete execution either without writing or reading flags Aug 29, 2021 Issued
Array ( [id] => 18965847 [patent_doc_number] => 11899613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-13 [patent_title] => Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging [patent_app_type] => utility [patent_app_number] => 17/408251 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 61 [patent_no_of_words] => 31584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408251 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408251
Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging Aug 19, 2021 Issued
Array ( [id] => 19443127 [patent_doc_number] => 12093392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Electronic-device control system and electronic-device control method [patent_app_type] => utility [patent_app_number] => 17/407169 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5343 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407169
Electronic-device control system and electronic-device control method Aug 18, 2021 Issued
Array ( [id] => 17260906 [patent_doc_number] => 20210373891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => ENHANCED PROTECTION OF PROCESSORS FROM A BUFFER OVERFLOW ATTACK [patent_app_type] => utility [patent_app_number] => 17/402117 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402117
Enhanced protection of processors from a buffer overflow attack Aug 12, 2021 Issued
Array ( [id] => 18154786 [patent_doc_number] => 11567764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Pre-staged instruction registers for variable length instruction set machine [patent_app_type] => utility [patent_app_number] => 17/401005 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11825 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401005
Pre-staged instruction registers for variable length instruction set machine Aug 11, 2021 Issued
Array ( [id] => 18154786 [patent_doc_number] => 11567764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Pre-staged instruction registers for variable length instruction set machine [patent_app_type] => utility [patent_app_number] => 17/401005 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11825 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401005
Pre-staged instruction registers for variable length instruction set machine Aug 11, 2021 Issued
Array ( [id] => 18154786 [patent_doc_number] => 11567764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Pre-staged instruction registers for variable length instruction set machine [patent_app_type] => utility [patent_app_number] => 17/401005 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11825 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401005
Pre-staged instruction registers for variable length instruction set machine Aug 11, 2021 Issued
Array ( [id] => 18154786 [patent_doc_number] => 11567764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Pre-staged instruction registers for variable length instruction set machine [patent_app_type] => utility [patent_app_number] => 17/401005 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11825 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401005
Pre-staged instruction registers for variable length instruction set machine Aug 11, 2021 Issued
Array ( [id] => 17230661 [patent_doc_number] => 20210357218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => METHOD AND APPARATUS FOR VECTOR SORTING [patent_app_type] => utility [patent_app_number] => 17/387260 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387260
Method and apparatus for vector sorting Jul 27, 2021 Issued
Array ( [id] => 18046772 [patent_doc_number] => 11520726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Host connected computer network [patent_app_type] => utility [patent_app_number] => 17/305762 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 15 [patent_no_of_words] => 18861 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305762
Host connected computer network Jul 13, 2021 Issued
Array ( [id] => 18122535 [patent_doc_number] => 20230008138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => PARALLEL PROCESSOR OPTIMIZED FOR MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 17/370995 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370995
Parallel processor optimized for machine learning Jul 7, 2021 Issued
Array ( [id] => 18104327 [patent_doc_number] => 11544213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Neural processor [patent_app_type] => utility [patent_app_number] => 17/369298 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9699 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369298 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369298
Neural processor Jul 6, 2021 Issued
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