Eliseo Ramos Feliciano

Array ( [id] => 2795240 [patent_doc_number] => 05165016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Image data output apparatus with display range designation means' [patent_app_type] => 1 [patent_app_number] => 7/469792 [patent_app_country] => US [patent_app_date] => 1990-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 3563 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/165/05165016.pdf [firstpage_image] =>[orig_patent_app_number] => 469792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2863713 [patent_doc_number] => 05126966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs' [patent_app_type] => 1 [patent_app_number] => 7/467297 [patent_app_country] => US [patent_app_date] => 1990-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1836 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126966.pdf [firstpage_image] =>[orig_patent_app_number] => 467297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3095194 [patent_doc_number] => 05280609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Methods of selecting document objects for documents stored in a folder format within an electronic information processing system' [patent_app_type] => 1 [patent_app_number] => 7/453089 [patent_app_country] => US [patent_app_date] => 1989-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3829 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280609.pdf [firstpage_image] =>[orig_patent_app_number] => 453089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3090331 [patent_doc_number] => 05297289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'System which cooperatively uses a systolic array processor and auxiliary processor for pixel signal enhancement' [patent_app_type] => 1 [patent_app_number] => 7/430835 [patent_app_country] => US [patent_app_date] => 1989-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5272 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 421 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297289.pdf [firstpage_image] =>[orig_patent_app_number] => 430835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2907726 [patent_doc_number] => 05241640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Disk unit with processors which detect cache status and control port selection for optimizing utilization of cache interfacing host and external memory' [patent_app_type] => 1 [patent_app_number] => 7/418659 [patent_app_country] => US [patent_app_date] => 1989-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4589 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241640.pdf [firstpage_image] =>[orig_patent_app_number] => 418659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2946636 [patent_doc_number] => 05230046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'System for independently controlling supply of a clock signal to a selected group of the arithmetic processors connected in series' [patent_app_type] => 1 [patent_app_number] => 7/419274 [patent_app_country] => US [patent_app_date] => 1989-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3891 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/230/05230046.pdf [firstpage_image] =>[orig_patent_app_number] => 419274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2889818 [patent_doc_number] => 05159683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Graphics controller adapted to automatically sense the type of connected video monitor and configure the control and display signals supplied to the monitor accordingly' [patent_app_type] => 1 [patent_app_number] => 7/405041 [patent_app_country] => US [patent_app_date] => 1989-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159683.pdf [firstpage_image] =>[orig_patent_app_number] => 405041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2931078 [patent_doc_number] => 05206949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Database search and record retrieval system which continuously displays category names during scrolling and selection of individually displayed search terms' [patent_app_type] => 1 [patent_app_number] => 7/390524 [patent_app_country] => US [patent_app_date] => 1989-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 13829 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206949.pdf [firstpage_image] =>[orig_patent_app_number] => 390524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2831377 [patent_doc_number] => 05095424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Computer system architecture implementing split instruction and operand cache line-pair-state management' [patent_app_type] => 1 [patent_app_number] => 7/384867 [patent_app_country] => US [patent_app_date] => 1989-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 9154 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/095/05095424.pdf [firstpage_image] =>[orig_patent_app_number] => 384867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2831413 [patent_doc_number] => 05095426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Data processing system for effectively handling exceptions during execution of two different types of instructions' [patent_app_type] => 1 [patent_app_number] => 7/361977 [patent_app_country] => US [patent_app_date] => 1989-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3929 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/095/05095426.pdf [firstpage_image] =>[orig_patent_app_number] => 361977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2947147 [patent_doc_number] => 05230073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'System and method for accessing and updating a continuously broadcasted stored database' [patent_app_type] => 1 [patent_app_number] => 7/363298 [patent_app_country] => US [patent_app_date] => 1989-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7765 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/230/05230073.pdf [firstpage_image] =>[orig_patent_app_number] => 363298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2882683 [patent_doc_number] => 05163132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Integrated controller using alternately filled and emptied buffers for controlling bi-directional data transfer between a processor and a data storage device' [patent_app_type] => 1 [patent_app_number] => 7/363352 [patent_app_country] => US [patent_app_date] => 1989-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2322 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/163/05163132.pdf [firstpage_image] =>[orig_patent_app_number] => 363352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3023947 [patent_doc_number] => 05276829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Data processing system including cache memory for rapidly converting a logical address into a physical address using shared memory flag' [patent_app_type] => 1 [patent_app_number] => 7/359281 [patent_app_country] => US [patent_app_date] => 1989-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4487 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 421 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276829.pdf [firstpage_image] =>[orig_patent_app_number] => 359281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2823514 [patent_doc_number] => 05079736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-07 [patent_title] => 'High speed pipeline merge sorter with run length tuning mechanism' [patent_app_type] => 1 [patent_app_number] => 7/357128 [patent_app_country] => US [patent_app_date] => 1989-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2052 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/079/05079736.pdf [firstpage_image] =>[orig_patent_app_number] => 357128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2678148 [patent_doc_number] => 05073854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Data processing system with search processor which initiates searching in response to predetermined disk read and write commands' [patent_app_type] => 1 [patent_app_number] => 7/352370 [patent_app_country] => US [patent_app_date] => 1989-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2619 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073854.pdf [firstpage_image] =>[orig_patent_app_number] => 352370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2934168 [patent_doc_number] => 05235685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Interface bus with independent data, command and direct control sections for parallel transfer of information between host and intelligent storage' [patent_app_type] => 1 [patent_app_number] => 7/350331 [patent_app_country] => US [patent_app_date] => 1989-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 52 [patent_no_of_words] => 5843 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235685.pdf [firstpage_image] =>[orig_patent_app_number] => 350331 [rel_patent_id] =>[rel_patent_doc_number] =>)