Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2888710 [patent_doc_number] => 05185867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Method and apparatus for automatically generating software specifications' [patent_app_type] => 1 [patent_app_number] => 7/323662 [patent_app_country] => US [patent_app_date] => 1989-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 4561 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185867.pdf [firstpage_image] =>[orig_patent_app_number] => 323662 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/323662
Method and apparatus for automatically generating software specifications Mar 14, 1989 Issued
Array ( [id] => 2980220 [patent_doc_number] => 05202978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Self-test circuit of information processor' [patent_app_type] => 1 [patent_app_number] => 7/323824 [patent_app_country] => US [patent_app_date] => 1989-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4754 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202978.pdf [firstpage_image] =>[orig_patent_app_number] => 323824 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/323824
Self-test circuit of information processor Mar 14, 1989 Issued
Array ( [id] => 2948735 [patent_doc_number] => 05247670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Network server' [patent_app_type] => 1 [patent_app_number] => 7/321134 [patent_app_country] => US [patent_app_date] => 1989-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5642 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247670.pdf [firstpage_image] =>[orig_patent_app_number] => 321134 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/321134
Network server Mar 8, 1989 Issued
Array ( [id] => 2849537 [patent_doc_number] => 05161216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'Interprocedural slicing of computer programs using dependence graphs' [patent_app_type] => 1 [patent_app_number] => 7/324321 [patent_app_country] => US [patent_app_date] => 1989-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15252 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/161/05161216.pdf [firstpage_image] =>[orig_patent_app_number] => 324321 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/324321
Interprocedural slicing of computer programs using dependence graphs Mar 7, 1989 Issued
Array ( [id] => 3503378 [patent_doc_number] => 05561787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'User interface module' [patent_app_type] => 1 [patent_app_number] => 7/320193 [patent_app_country] => US [patent_app_date] => 1989-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3938 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561787.pdf [firstpage_image] =>[orig_patent_app_number] => 320193 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/320193
User interface module Mar 6, 1989 Issued
Array ( [id] => 2939928 [patent_doc_number] => 05187798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Electronic postage meter having separate funds charge registers and recredits funds register in predetermined amount when funds fall to predetermined level' [patent_app_type] => 1 [patent_app_number] => 7/319456 [patent_app_country] => US [patent_app_date] => 1989-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3028 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/187/05187798.pdf [firstpage_image] =>[orig_patent_app_number] => 319456 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/319456
Electronic postage meter having separate funds charge registers and recredits funds register in predetermined amount when funds fall to predetermined level Mar 5, 1989 Issued
Array ( [id] => 2844079 [patent_doc_number] => 05129085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Computer network with shared memory using bit maps including flags to indicate reserved memory areas and task status' [patent_app_type] => 1 [patent_app_number] => 7/318750 [patent_app_country] => US [patent_app_date] => 1989-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3055 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/129/05129085.pdf [firstpage_image] =>[orig_patent_app_number] => 318750 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/318750
Computer network with shared memory using bit maps including flags to indicate reserved memory areas and task status Mar 2, 1989 Issued
Array ( [id] => 2849775 [patent_doc_number] => 05161228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'System with selectively exclusionary enablement for plural indirect address type interrupt control circuit' [patent_app_type] => 1 [patent_app_number] => 7/317808 [patent_app_country] => US [patent_app_date] => 1989-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6680 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/161/05161228.pdf [firstpage_image] =>[orig_patent_app_number] => 317808 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/317808
System with selectively exclusionary enablement for plural indirect address type interrupt control circuit Mar 1, 1989 Issued
Array ( [id] => 2988917 [patent_doc_number] => 05226157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Backup control method and system in data processing system using identifiers for controlling block data transfer' [patent_app_type] => 1 [patent_app_number] => 7/318006 [patent_app_country] => US [patent_app_date] => 1989-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4527 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226157.pdf [firstpage_image] =>[orig_patent_app_number] => 318006 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/318006
Backup control method and system in data processing system using identifiers for controlling block data transfer Mar 1, 1989 Issued
Array ( [id] => 2770029 [patent_doc_number] => 05060188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-22 [patent_title] => 'System using registers for maintaining data address and class information from previous module accesses for predictive memory module selection' [patent_app_type] => 1 [patent_app_number] => 7/316068 [patent_app_country] => US [patent_app_date] => 1989-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3757 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/060/05060188.pdf [firstpage_image] =>[orig_patent_app_number] => 316068 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/316068
System using registers for maintaining data address and class information from previous module accesses for predictive memory module selection Feb 26, 1989 Issued
Array ( [id] => 2881148 [patent_doc_number] => 05091853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Chained addressing mode pipelined processor which merges separately decoded parts of a multiple operation instruction' [patent_app_type] => 1 [patent_app_number] => 7/314727 [patent_app_country] => US [patent_app_date] => 1989-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 36 [patent_no_of_words] => 14910 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091853.pdf [firstpage_image] =>[orig_patent_app_number] => 314727 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/314727
Chained addressing mode pipelined processor which merges separately decoded parts of a multiple operation instruction Feb 21, 1989 Issued
Array ( [id] => 2872682 [patent_doc_number] => 05167025 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Programmable controller generating plural alternating clocks with each clock controlling different parts of instruction sequencing mechanism' [patent_app_type] => 1 [patent_app_number] => 7/313562 [patent_app_country] => US [patent_app_date] => 1989-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1921 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/167/05167025.pdf [firstpage_image] =>[orig_patent_app_number] => 313562 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/313562
Programmable controller generating plural alternating clocks with each clock controlling different parts of instruction sequencing mechanism Feb 21, 1989 Issued
Array ( [id] => 2799762 [patent_doc_number] => 05155852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Digital information coding system which evenly distributes valid input data to digital signal processors operating in parallel' [patent_app_type] => 1 [patent_app_number] => 7/311815 [patent_app_country] => US [patent_app_date] => 1989-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 12688 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155852.pdf [firstpage_image] =>[orig_patent_app_number] => 311815 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/311815
Digital information coding system which evenly distributes valid input data to digital signal processors operating in parallel Feb 16, 1989 Issued
Array ( [id] => 2892010 [patent_doc_number] => 05119491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'Method and apparatus for formatting document by using command codes regarding document structure' [patent_app_type] => 1 [patent_app_number] => 7/309128 [patent_app_country] => US [patent_app_date] => 1989-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3122 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/119/05119491.pdf [firstpage_image] =>[orig_patent_app_number] => 309128 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/309128
Method and apparatus for formatting document by using command codes regarding document structure Feb 12, 1989 Issued
Array ( [id] => 2842855 [patent_doc_number] => 05175828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Method and apparatus for dynamically linking subprogram to main program using tabled procedure name comparison' [patent_app_type] => 1 [patent_app_number] => 7/310270 [patent_app_country] => US [patent_app_date] => 1989-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3426 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175828.pdf [firstpage_image] =>[orig_patent_app_number] => 310270 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/310270
Method and apparatus for dynamically linking subprogram to main program using tabled procedure name comparison Feb 12, 1989 Issued
Array ( [id] => 2864129 [patent_doc_number] => 05134701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Test apparatus performing runtime replacement of program instructions with breakpoint instructions for processor having multiple instruction fetch capabilities' [patent_app_type] => 1 [patent_app_number] => 7/310153 [patent_app_country] => US [patent_app_date] => 1989-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3539 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134701.pdf [firstpage_image] =>[orig_patent_app_number] => 310153 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/310153
Test apparatus performing runtime replacement of program instructions with breakpoint instructions for processor having multiple instruction fetch capabilities Feb 9, 1989 Issued
07/308041 MICROCODE ENTRY TABLE SIZE REDUCTION APPARATUS AND METHOD Feb 7, 1989 Abandoned
Array ( [id] => 2899508 [patent_doc_number] => 05214767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes' [patent_app_type] => 1 [patent_app_number] => 7/307773 [patent_app_country] => US [patent_app_date] => 1989-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11427 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/214/05214767.pdf [firstpage_image] =>[orig_patent_app_number] => 307773 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/307773
Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes Feb 6, 1989 Issued
Array ( [id] => 2867657 [patent_doc_number] => 05113515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer' [patent_app_type] => 1 [patent_app_number] => 7/306831 [patent_app_country] => US [patent_app_date] => 1989-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12279 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/113/05113515.pdf [firstpage_image] =>[orig_patent_app_number] => 306831 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/306831
Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer Feb 2, 1989 Issued
Array ( [id] => 2797529 [patent_doc_number] => 05142622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'System for interconnecting applications across different networks of data processing systems by mapping protocols across different network domains' [patent_app_type] => 1 [patent_app_number] => 7/304696 [patent_app_country] => US [patent_app_date] => 1989-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5950 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142622.pdf [firstpage_image] =>[orig_patent_app_number] => 304696 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/304696
System for interconnecting applications across different networks of data processing systems by mapping protocols across different network domains Jan 30, 1989 Issued
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