Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2892581 [patent_doc_number] => 05109497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Arithmetic element controller for controlling data, control and micro store memories' [patent_app_type] => 1 [patent_app_number] => 7/303786 [patent_app_country] => US [patent_app_date] => 1989-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5852 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109497.pdf [firstpage_image] =>[orig_patent_app_number] => 303786 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/303786
Arithmetic element controller for controlling data, control and micro store memories Jan 26, 1989 Issued
Array ( [id] => 2718666 [patent_doc_number] => 05018060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-21 [patent_title] => 'Allocating data storage space of peripheral data storage devices using implied allocation based on user parameters' [patent_app_type] => 1 [patent_app_number] => 7/301970 [patent_app_country] => US [patent_app_date] => 1989-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 8866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/018/05018060.pdf [firstpage_image] =>[orig_patent_app_number] => 301970 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/301970
Allocating data storage space of peripheral data storage devices using implied allocation based on user parameters Jan 25, 1989 Issued
07/301952 DOCUMENT PROCESSING APPARATUS FOR DISPLAYING INPUTTED DATA IN A PRINT AREA BASED UPON THE SIZE OF A RECORDING MATERIAL AND THE PREPRINTED DATA PRINTED THEREON Jan 25, 1989 Abandoned
07/299759 VARIABLE LENGTH STRING MATCHER Jan 22, 1989 Abandoned
Array ( [id] => 2765478 [patent_doc_number] => 05043880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-27 [patent_title] => 'Data flow processor which combines packets having same identification and destination and synchronizes loop variables for detecting processing loop termination' [patent_app_type] => 1 [patent_app_number] => 7/299626 [patent_app_country] => US [patent_app_date] => 1989-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4450 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/043/05043880.pdf [firstpage_image] =>[orig_patent_app_number] => 299626 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/299626
Data flow processor which combines packets having same identification and destination and synchronizes loop variables for detecting processing loop termination Jan 22, 1989 Issued
Array ( [id] => 2800233 [patent_doc_number] => 05101496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Printer interface system which selectively receives horizontal sync signal and dot clock signals from plural printing image data' [patent_app_type] => 1 [patent_app_number] => 7/299193 [patent_app_country] => US [patent_app_date] => 1989-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3277 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/101/05101496.pdf [firstpage_image] =>[orig_patent_app_number] => 299193 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/299193
Printer interface system which selectively receives horizontal sync signal and dot clock signals from plural printing image data Jan 18, 1989 Issued
Array ( [id] => 2961469 [patent_doc_number] => 05222217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'System and method for implementing operating system message queues with recoverable shared virtual storage' [patent_app_type] => 1 [patent_app_number] => 7/298384 [patent_app_country] => US [patent_app_date] => 1989-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 9695 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222217.pdf [firstpage_image] =>[orig_patent_app_number] => 298384 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/298384
System and method for implementing operating system message queues with recoverable shared virtual storage Jan 17, 1989 Issued
Array ( [id] => 2925387 [patent_doc_number] => 05237676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device' [patent_app_type] => 1 [patent_app_number] => 7/297773 [patent_app_country] => US [patent_app_date] => 1989-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6210 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237676.pdf [firstpage_image] =>[orig_patent_app_number] => 297773 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/297773
High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device Jan 12, 1989 Issued
Array ( [id] => 2939669 [patent_doc_number] => 05187784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram' [patent_app_type] => 1 [patent_app_number] => 7/297353 [patent_app_country] => US [patent_app_date] => 1989-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 2606 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/187/05187784.pdf [firstpage_image] =>[orig_patent_app_number] => 297353 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/297353
Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram Jan 12, 1989 Issued
Array ( [id] => 2827081 [patent_doc_number] => 05081609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-14 [patent_title] => 'Multiprocessor controller having time shared control store' [patent_app_type] => 1 [patent_app_number] => 7/295629 [patent_app_country] => US [patent_app_date] => 1989-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 7 [patent_no_of_words] => 4689 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/081/05081609.pdf [firstpage_image] =>[orig_patent_app_number] => 295629 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/295629
Multiprocessor controller having time shared control store Jan 9, 1989 Issued
Array ( [id] => 2939832 [patent_doc_number] => 05187793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache' [patent_app_type] => 1 [patent_app_number] => 7/294888 [patent_app_country] => US [patent_app_date] => 1989-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2842 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/187/05187793.pdf [firstpage_image] =>[orig_patent_app_number] => 294888 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/294888
Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache Jan 8, 1989 Issued
Array ( [id] => 2818236 [patent_doc_number] => 05148533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units' [patent_app_type] => 1 [patent_app_number] => 7/294534 [patent_app_country] => US [patent_app_date] => 1989-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 7 [patent_no_of_words] => 8209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148533.pdf [firstpage_image] =>[orig_patent_app_number] => 294534 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/294534
Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units Jan 4, 1989 Issued
07/294075 CIRCUIT INCLUDING COMMUNICATION CIRCUITRY Jan 4, 1989 Abandoned
Array ( [id] => 2742741 [patent_doc_number] => 05051894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Apparatus and method for address translation of non-aligned double word virtual addresses' [patent_app_type] => 1 [patent_app_number] => 7/294528 [patent_app_country] => US [patent_app_date] => 1989-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 6 [patent_no_of_words] => 6259 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051894.pdf [firstpage_image] =>[orig_patent_app_number] => 294528 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/294528
Apparatus and method for address translation of non-aligned double word virtual addresses Jan 4, 1989 Issued
Array ( [id] => 2963493 [patent_doc_number] => 05263148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Method and apparatus for configuration of computer system and circuit boards' [patent_app_type] => 1 [patent_app_number] => 7/293315 [patent_app_country] => US [patent_app_date] => 1989-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 14255 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/263/05263148.pdf [firstpage_image] =>[orig_patent_app_number] => 293315 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/293315
Method and apparatus for configuration of computer system and circuit boards Jan 3, 1989 Issued
Array ( [id] => 2877054 [patent_doc_number] => 05097410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Multimode data system for transferring control and data information in an I/O subsystem' [patent_app_type] => 1 [patent_app_number] => 7/292399 [patent_app_country] => US [patent_app_date] => 1988-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 17172 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/097/05097410.pdf [firstpage_image] =>[orig_patent_app_number] => 292399 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/292399
Multimode data system for transferring control and data information in an I/O subsystem Dec 29, 1988 Issued
07/292666 APPARATUS FOR SELECTIVELY TRANSLATING TEXT CONTAINED WITHIN COMPUTER SOFTWARE AND INTENDED FOR OUTPUT TO A USER Dec 29, 1988 Abandoned
Array ( [id] => 2817231 [patent_doc_number] => 05146587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'System with simultaneous storage of multilingual error messages in plural loop connected processors for transmission automatic translation and message display' [patent_app_type] => 1 [patent_app_number] => 7/292060 [patent_app_country] => US [patent_app_date] => 1988-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 12407 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146587.pdf [firstpage_image] =>[orig_patent_app_number] => 292060 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/292060
System with simultaneous storage of multilingual error messages in plural loop connected processors for transmission automatic translation and message display Dec 29, 1988 Issued
Array ( [id] => 2864914 [patent_doc_number] => 05113370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'Instruction buffer control system using buffer partitions and selective instruction replacement for processing large instruction loops' [patent_app_type] => 1 [patent_app_number] => 7/289564 [patent_app_country] => US [patent_app_date] => 1988-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2049 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/113/05113370.pdf [firstpage_image] =>[orig_patent_app_number] => 289564 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/289564
Instruction buffer control system using buffer partitions and selective instruction replacement for processing large instruction loops Dec 22, 1988 Issued
07/289198 MICROCONTROLLER PERIPHERAL EXPANSION BUS Dec 22, 1988 Abandoned
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