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Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2799824 [patent_doc_number] => 05155855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Multi-CPU system using common memory and having access mediation latch' [patent_app_type] => 1 [patent_app_number] => 7/262908 [patent_app_country] => US [patent_app_date] => 1988-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 61 [patent_no_of_words] => 5450 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155855.pdf [firstpage_image] =>[orig_patent_app_number] => 262908 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/262908
Multi-CPU system using common memory and having access mediation latch Oct 25, 1988 Issued
Array ( [id] => 2815869 [patent_doc_number] => 05115510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information' [patent_app_type] => 1 [patent_app_number] => 7/259722 [patent_app_country] => US [patent_app_date] => 1988-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6873 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115510.pdf [firstpage_image] =>[orig_patent_app_number] => 259722 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/259722
Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information Oct 18, 1988 Issued
Array ( [id] => 2815587 [patent_doc_number] => 05115495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Communications network system using full-juncture and partial-juncture station status information for alternate-path distance-vector routing' [patent_app_type] => 1 [patent_app_number] => 7/259329 [patent_app_country] => US [patent_app_date] => 1988-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 9885 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115495.pdf [firstpage_image] =>[orig_patent_app_number] => 259329 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/259329
Communications network system using full-juncture and partial-juncture station status information for alternate-path distance-vector routing Oct 17, 1988 Issued
Array ( [id] => 2877085 [patent_doc_number] => 05097411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Graphics workstation for creating graphics data structure which are stored retrieved and displayed by a graphics subsystem for competing programs' [patent_app_type] => 1 [patent_app_number] => 7/258398 [patent_app_country] => US [patent_app_date] => 1988-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 25229 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/097/05097411.pdf [firstpage_image] =>[orig_patent_app_number] => 258398 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/258398
Graphics workstation for creating graphics data structure which are stored retrieved and displayed by a graphics subsystem for competing programs Oct 16, 1988 Issued
Array ( [id] => 2742579 [patent_doc_number] => 05051885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Data processing system for concurrent dispatch of instructions to multiple functional units' [patent_app_type] => 1 [patent_app_number] => 7/255105 [patent_app_country] => US [patent_app_date] => 1988-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3962 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051885.pdf [firstpage_image] =>[orig_patent_app_number] => 255105 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/255105
Data processing system for concurrent dispatch of instructions to multiple functional units Oct 6, 1988 Issued
07/254718 PARALLEL DATA PROCESSOR Oct 6, 1988 Abandoned
Array ( [id] => 2889949 [patent_doc_number] => 05159690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Multidimensional cellular data array processing system which separately permutes stored data elements and applies transformation rules to permuted elements' [patent_app_type] => 1 [patent_app_number] => 7/252391 [patent_app_country] => US [patent_app_date] => 1988-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7374 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159690.pdf [firstpage_image] =>[orig_patent_app_number] => 252391 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/252391
Multidimensional cellular data array processing system which separately permutes stored data elements and applies transformation rules to permuted elements Sep 29, 1988 Issued
Array ( [id] => 2799106 [patent_doc_number] => 05155818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Unconditional wide branch instruction acceleration' [patent_app_type] => 1 [patent_app_number] => 7/250355 [patent_app_country] => US [patent_app_date] => 1988-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2979 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155818.pdf [firstpage_image] =>[orig_patent_app_number] => 250355 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/250355
Unconditional wide branch instruction acceleration Sep 27, 1988 Issued
07/248835 FLEXIBLE SCOPE EDITING METHOD IN A STRUCTURE EDITOR Sep 25, 1988 Abandoned
Array ( [id] => 2815723 [patent_doc_number] => 05115502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Method and apparatus for determining internal status of a processor using simulation guided by acquired data' [patent_app_type] => 1 [patent_app_number] => 7/246046 [patent_app_country] => US [patent_app_date] => 1988-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8254 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115502.pdf [firstpage_image] =>[orig_patent_app_number] => 246046 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/246046
Method and apparatus for determining internal status of a processor using simulation guided by acquired data Sep 18, 1988 Issued
07/245978 HIGH PERFORMANCE INSTRUCTION-EMULATION IN A LARGE SCALE DATA PROCESSING SYSTEM Sep 18, 1988 Abandoned
07/244503 DIRECTOR COMPRISING CONTROL ARRANGEMENT FOR CONTROLLING AND MONITORING ENTITIES IN COMPLEX SYSTEM Sep 12, 1988 Abandoned
07/244506 CONTROLLABLE ENTITY FOR USE IN COMPLEX SYSTEM Sep 11, 1988 Abandoned
07/242734 METHOD AND APPARATUS FOR CONFIGURATION OF COMPUTER SYSTEM AND CIRCUIT BOARDS Sep 8, 1988 Abandoned
07/242140 ADDRESS/CONTROL SIGNAL INPUT CIRCUIT FOR CACHE CONTROLLER Sep 7, 1988 Abandoned
Array ( [id] => 2716629 [patent_doc_number] => 05062039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Sharing of workspaces in interactive processing using workspace name tables for linking of workspaces' [patent_app_type] => 1 [patent_app_number] => 7/241496 [patent_app_country] => US [patent_app_date] => 1988-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5905 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/062/05062039.pdf [firstpage_image] =>[orig_patent_app_number] => 241496 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/241496
Sharing of workspaces in interactive processing using workspace name tables for linking of workspaces Sep 6, 1988 Issued
Array ( [id] => 2797210 [patent_doc_number] => 05101341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO' [patent_app_type] => 1 [patent_app_number] => 7/241111 [patent_app_country] => US [patent_app_date] => 1988-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8439 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/101/05101341.pdf [firstpage_image] =>[orig_patent_app_number] => 241111 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/241111
Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO Sep 1, 1988 Issued
07/239202 DATA PROCESS SYSTEM AND METHOD FOR MULTIPLE MODE ACCESS OF VARIABLE BIT LENGTH DATA Aug 29, 1988 Abandoned
Array ( [id] => 2817833 [patent_doc_number] => 05148516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Efficient computer terminal system utilizing a single slave processor' [patent_app_type] => 1 [patent_app_number] => 7/238235 [patent_app_country] => US [patent_app_date] => 1988-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1581 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148516.pdf [firstpage_image] =>[orig_patent_app_number] => 238235 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/238235
Efficient computer terminal system utilizing a single slave processor Aug 29, 1988 Issued
Array ( [id] => 2892616 [patent_doc_number] => 05109499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Vector multiprocessor system which individually indicates the data element stored in common vector register' [patent_app_type] => 1 [patent_app_number] => 7/237418 [patent_app_country] => US [patent_app_date] => 1988-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11043 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109499.pdf [firstpage_image] =>[orig_patent_app_number] => 237418 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/237418
Vector multiprocessor system which individually indicates the data element stored in common vector register Aug 28, 1988 Issued
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