Eliseo Ramos Feliciano

Array ( [id] => 2857974 [patent_doc_number] => 05111390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Software security system for maintaining integrity of compiled object code by restricting users ability to define compilers' [patent_app_type] => 1 [patent_app_number] => 7/234772 [patent_app_country] => US [patent_app_date] => 1988-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4634 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111390.pdf [firstpage_image] =>[orig_patent_app_number] => 234772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2703164 [patent_doc_number] => 04996665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Method and device for editing a document having a plurality of headings' [patent_app_type] => 1 [patent_app_number] => 7/227653 [patent_app_country] => US [patent_app_date] => 1988-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4871 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996665.pdf [firstpage_image] =>[orig_patent_app_number] => 227653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2680345 [patent_doc_number] => 05073969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal' [patent_app_type] => 1 [patent_app_number] => 7/227078 [patent_app_country] => US [patent_app_date] => 1988-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4932 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073969.pdf [firstpage_image] =>[orig_patent_app_number] => 227078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2892835 [patent_doc_number] => 05109510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'System concurrently running application programs and selectively routing device input to resource controller created virtual terminals and real physical devices' [patent_app_type] => 1 [patent_app_number] => 7/225630 [patent_app_country] => US [patent_app_date] => 1988-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5196 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109510.pdf [firstpage_image] =>[orig_patent_app_number] => 225630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2798543 [patent_doc_number] => 05142670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Method and apparatus for calculating disk-access footprints for use in selecting a storage management method' [patent_app_type] => 1 [patent_app_number] => 7/224845 [patent_app_country] => US [patent_app_date] => 1988-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4528 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142670.pdf [firstpage_image] =>[orig_patent_app_number] => 224845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2850132 [patent_doc_number] => 05121496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Method for creating, maintaining and using an expert system by recursively modifying calibration file and merging with standard file' [patent_app_type] => 1 [patent_app_number] => 7/224508 [patent_app_country] => US [patent_app_date] => 1988-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2760 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121496.pdf [firstpage_image] =>[orig_patent_app_number] => 224508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2818293 [patent_doc_number] => 05148536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Pipeline having an integral cache which processes cache misses and loads data in parallel' [patent_app_type] => 1 [patent_app_number] => 7/224483 [patent_app_country] => US [patent_app_date] => 1988-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 9710 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148536.pdf [firstpage_image] =>[orig_patent_app_number] => 224483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2858555 [patent_doc_number] => 05111423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Programmable interface for computer system peripheral circuit card' [patent_app_type] => 1 [patent_app_number] => 7/222565 [patent_app_country] => US [patent_app_date] => 1988-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8307 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111423.pdf [firstpage_image] =>[orig_patent_app_number] => 222565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2899746 [patent_doc_number] => 05214779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Variable construct representation embedded in data stream which references definition for dynamically generating data used in processing the data stream' [patent_app_type] => 1 [patent_app_number] => 7/213425 [patent_app_country] => US [patent_app_date] => 1988-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1779 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/214/05214779.pdf [firstpage_image] =>[orig_patent_app_number] => 213425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2803807 [patent_doc_number] => 05136696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions' [patent_app_type] => 1 [patent_app_number] => 7/211977 [patent_app_country] => US [patent_app_date] => 1988-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8764 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/136/05136696.pdf [firstpage_image] =>[orig_patent_app_number] => 211977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2864091 [patent_doc_number] => 05134699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Programmable burst data transfer apparatus and technique' [patent_app_type] => 1 [patent_app_number] => 7/211357 [patent_app_country] => US [patent_app_date] => 1988-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 9004 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134699.pdf [firstpage_image] =>[orig_patent_app_number] => 211357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2797341 [patent_doc_number] => 05101348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Method of reducing the amount of information included in topology database update messages in a data communications network' [patent_app_type] => 1 [patent_app_number] => 7/210251 [patent_app_country] => US [patent_app_date] => 1988-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5725 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/101/05101348.pdf [firstpage_image] =>[orig_patent_app_number] => 210251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2933992 [patent_doc_number] => 05201040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Multiprocessor system having subsystems which are loosely coupled through a random access storage and which each include a tightly coupled multiprocessor' [patent_app_type] => 1 [patent_app_number] => 7/209073 [patent_app_country] => US [patent_app_date] => 1988-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/201/05201040.pdf [firstpage_image] =>[orig_patent_app_number] => 209073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2915508 [patent_doc_number] => 05249276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Address translation apparatus having a memory access privilege check capability data which uses mask data to select bit positions of priviledge' [patent_app_type] => 1 [patent_app_number] => 7/208493 [patent_app_country] => US [patent_app_date] => 1988-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6022 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249276.pdf [firstpage_image] =>[orig_patent_app_number] => 208493 [rel_patent_id] =>[rel_patent_doc_number] =>)