Eliseo Ramos Feliciano

Array ( [id] => 2787709 [patent_doc_number] => 05151986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-29 [patent_title] => 'Microcomputer with on-board chip selects and programmable bus stretching' [patent_app_type] => 1 [patent_app_number] => 7/090180 [patent_app_country] => US [patent_app_date] => 1987-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3115 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/151/05151986.pdf [firstpage_image] =>[orig_patent_app_number] => 090180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2715937 [patent_doc_number] => 05014194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'System for reducing I/O controller overhead by using a peripheral controller for producing read, write, and address translation request signals' [patent_app_type] => 1 [patent_app_number] => 7/089785 [patent_app_country] => US [patent_app_date] => 1987-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5759 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 494 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/014/05014194.pdf [firstpage_image] =>[orig_patent_app_number] => 089785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2988274 [patent_doc_number] => 05226122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Programmable logic system for filtering commands to a microprocessor' [patent_app_type] => 1 [patent_app_number] => 7/088093 [patent_app_country] => US [patent_app_date] => 1987-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4816 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226122.pdf [firstpage_image] =>[orig_patent_app_number] => 088093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2856991 [patent_doc_number] => 05107420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'Synchronous apparatus for processors' [patent_app_type] => 1 [patent_app_number] => 7/084804 [patent_app_country] => US [patent_app_date] => 1987-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2256 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/107/05107420.pdf [firstpage_image] =>[orig_patent_app_number] => 084804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2677638 [patent_doc_number] => 04999770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-12 [patent_title] => 'Command controlled multi-storage space protection key pretesting system permitting access regardless of test result if selected key is predetermined value' [patent_app_type] => 1 [patent_app_number] => 7/084092 [patent_app_country] => US [patent_app_date] => 1987-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3833 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/999/04999770.pdf [firstpage_image] =>[orig_patent_app_number] => 084092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2589335 [patent_doc_number] => 04974198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-27 [patent_title] => 'Vector processing system utilizing firm ware control to prevent delays during processing operations' [patent_app_type] => 1 [patent_app_number] => 7/073728 [patent_app_country] => US [patent_app_date] => 1987-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5469 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/974/04974198.pdf [firstpage_image] =>[orig_patent_app_number] => 073728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2577870 [patent_doc_number] => 04901228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-13 [patent_title] => 'Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processing' [patent_app_type] => 1 [patent_app_number] => 7/073513 [patent_app_country] => US [patent_app_date] => 1987-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4957 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/901/04901228.pdf [firstpage_image] =>[orig_patent_app_number] => 073513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2927837 [patent_doc_number] => 05179688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Queue system with uninterrupted transfer of data through intermediate locations to selected queue location' [patent_app_type] => 1 [patent_app_number] => 7/068699 [patent_app_country] => US [patent_app_date] => 1987-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2966 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179688.pdf [firstpage_image] =>[orig_patent_app_number] => 068699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2565752 [patent_doc_number] => 04942524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-17 [patent_title] => 'Software trap system which saves previous content of software trap handling pointer in a stack upon execution of a trap' [patent_app_type] => 1 [patent_app_number] => 7/065778 [patent_app_country] => US [patent_app_date] => 1987-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3798 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/942/04942524.pdf [firstpage_image] =>[orig_patent_app_number] => 065778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2716550 [patent_doc_number] => 05062035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Time slot allocation for loop networks' [patent_app_type] => 1 [patent_app_number] => 7/064652 [patent_app_country] => US [patent_app_date] => 1987-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 8652 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/062/05062035.pdf [firstpage_image] =>[orig_patent_app_number] => 064652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2799384 [patent_doc_number] => 05155833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory' [patent_app_type] => 1 [patent_app_number] => 7/048151 [patent_app_country] => US [patent_app_date] => 1987-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2331 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155833.pdf [firstpage_image] =>[orig_patent_app_number] => 048151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2601351 [patent_doc_number] => 04941083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-10 [patent_title] => 'Method and apparatus for initiating interlock read transactions on a multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 7/044486 [patent_app_country] => US [patent_app_date] => 1987-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9770 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/941/04941083.pdf [firstpage_image] =>[orig_patent_app_number] => 044486 [rel_patent_id] =>[rel_patent_doc_number] =>)