Eliseo Ramos Feliciano

Array ( [id] => 2421358 [patent_doc_number] => 04787029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-22 [patent_title] => 'Level converting bus extender with subsystem selection signal decoding enabling connection to microprocessor' [patent_app_type] => 1 [patent_app_number] => 6/912304 [patent_app_country] => US [patent_app_date] => 1986-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1759 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/787/04787029.pdf [firstpage_image] =>[orig_patent_app_number] => 912304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2482021 [patent_doc_number] => 04879648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-07 [patent_title] => 'Search system which continuously displays search terms during scrolling and selections of individually displayed data sets' [patent_app_type] => 1 [patent_app_number] => 6/909293 [patent_app_country] => US [patent_app_date] => 1986-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 13816 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/879/04879648.pdf [firstpage_image] =>[orig_patent_app_number] => 909293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2716728 [patent_doc_number] => 05014234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'System with software usage timer and counter for allowing limited use but preventing continued unauthorized use of protected software' [patent_app_type] => 1 [patent_app_number] => 6/900206 [patent_app_country] => US [patent_app_date] => 1986-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4227 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/014/05014234.pdf [firstpage_image] =>[orig_patent_app_number] => 900206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2461709 [patent_doc_number] => 04766566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-23 [patent_title] => 'Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing' [patent_app_type] => 1 [patent_app_number] => 6/896156 [patent_app_country] => US [patent_app_date] => 1986-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5303 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/766/04766566.pdf [firstpage_image] =>[orig_patent_app_number] => 896156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2395917 [patent_doc_number] => 04764866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-16 [patent_title] => 'Data processing system with pre-decoding of op codes' [patent_app_type] => 1 [patent_app_number] => 6/894070 [patent_app_country] => US [patent_app_date] => 1986-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1906 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/764/04764866.pdf [firstpage_image] =>[orig_patent_app_number] => 894070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2464966 [patent_doc_number] => 04785395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-15 [patent_title] => 'Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement' [patent_app_type] => 1 [patent_app_number] => 6/879864 [patent_app_country] => US [patent_app_date] => 1986-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 4 [patent_no_of_words] => 5511 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/785/04785395.pdf [firstpage_image] =>[orig_patent_app_number] => 879864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2421998 [patent_doc_number] => 04787061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-22 [patent_title] => 'Dual delay mode pipelined logic simulator' [patent_app_type] => 1 [patent_app_number] => 6/878459 [patent_app_country] => US [patent_app_date] => 1986-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3016 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/787/04787061.pdf [firstpage_image] =>[orig_patent_app_number] => 878459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2721263 [patent_doc_number] => 05010476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-23 [patent_title] => 'Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units' [patent_app_type] => 1 [patent_app_number] => 6/876625 [patent_app_country] => US [patent_app_date] => 1986-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5711 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/010/05010476.pdf [firstpage_image] =>[orig_patent_app_number] => 876625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2565179 [patent_doc_number] => 04815032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-21 [patent_title] => 'Portable electronic memorandum device with password accessible memory' [patent_app_type] => 1 [patent_app_number] => 6/867244 [patent_app_country] => US [patent_app_date] => 1986-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4980 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/815/04815032.pdf [firstpage_image] =>[orig_patent_app_number] => 867244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2501927 [patent_doc_number] => 04825403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-25 [patent_title] => 'Apparatus guaranteeing that a controller in a disk drive system receives at least some data from an invalid track sector' [patent_app_type] => 1 [patent_app_number] => 6/858540 [patent_app_country] => US [patent_app_date] => 1986-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 28147 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/825/04825403.pdf [firstpage_image] =>[orig_patent_app_number] => 858540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2955456 [patent_doc_number] => 05224209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'System for choosing between operation modes in a data processing system by interacting with a displayed a multinodal hierarchal figure' [patent_app_type] => 1 [patent_app_number] => 6/854946 [patent_app_country] => US [patent_app_date] => 1986-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1790 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/224/05224209.pdf [firstpage_image] =>[orig_patent_app_number] => 854946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2864147 [patent_doc_number] => 05134702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Serial-to-parallel and parallel-to-serial converter' [patent_app_type] => 1 [patent_app_number] => 6/854380 [patent_app_country] => US [patent_app_date] => 1986-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6074 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134702.pdf [firstpage_image] =>[orig_patent_app_number] => 854380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2892336 [patent_doc_number] => 05109484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Self configuring terminal which polls loop network and generates list of connected devices for use in selectively downloading control programs' [patent_app_type] => 1 [patent_app_number] => 6/849641 [patent_app_country] => US [patent_app_date] => 1986-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3109 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109484.pdf [firstpage_image] =>[orig_patent_app_number] => 849641 [rel_patent_id] =>[rel_patent_doc_number] =>)