Eliseo Ramos Feliciano

Array ( [id] => 2795660 [patent_doc_number] => 05165039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Register file for bit slice processor with simultaneous accessing of plural memory array cells' [patent_app_type] => 1 [patent_app_number] => 6/845725 [patent_app_country] => US [patent_app_date] => 1986-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 7118 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/165/05165039.pdf [firstpage_image] =>[orig_patent_app_number] => 845725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2679339 [patent_doc_number] => 05034884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'System providing key scan key address extraction and bitwise signal transmission between input unit and signal processing unit in parallel' [patent_app_type] => 1 [patent_app_number] => 6/844122 [patent_app_country] => US [patent_app_date] => 1986-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5605 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034884.pdf [firstpage_image] =>[orig_patent_app_number] => 844122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2563889 [patent_doc_number] => 04809164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-28 [patent_title] => 'Processor controlled modifying of tabled input/output priority' [patent_app_type] => 1 [patent_app_number] => 6/844911 [patent_app_country] => US [patent_app_date] => 1986-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3829 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/809/04809164.pdf [firstpage_image] =>[orig_patent_app_number] => 844911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2704865 [patent_doc_number] => 04991080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-05 [patent_title] => 'Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions' [patent_app_type] => 1 [patent_app_number] => 6/839312 [patent_app_country] => US [patent_app_date] => 1986-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 13676 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/991/04991080.pdf [firstpage_image] =>[orig_patent_app_number] => 839312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2634440 [patent_doc_number] => 04920534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-24 [patent_title] => 'System for controllably eliminating bits from packet information field based on indicator in header and amount of data in packet buffer' [patent_app_type] => 1 [patent_app_number] => 6/834904 [patent_app_country] => US [patent_app_date] => 1986-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 21400 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/920/04920534.pdf [firstpage_image] =>[orig_patent_app_number] => 834904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2450739 [patent_doc_number] => 04779196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-18 [patent_title] => 'Interface device for controlling command and data transfer between a host computer and a disk controller' [patent_app_type] => 1 [patent_app_number] => 6/831695 [patent_app_country] => US [patent_app_date] => 1986-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3671 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/779/04779196.pdf [firstpage_image] =>[orig_patent_app_number] => 831695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2790044 [patent_doc_number] => 05088031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-11 [patent_title] => 'Virtual machine file control system which translates block numbers into virtual addresses then into real addresses for accessing main storage' [patent_app_type] => 1 [patent_app_number] => 6/827607 [patent_app_country] => US [patent_app_date] => 1986-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 9128 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/088/05088031.pdf [firstpage_image] =>[orig_patent_app_number] => 827607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2523246 [patent_doc_number] => 04851987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-25 [patent_title] => 'System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur' [patent_app_type] => 1 [patent_app_number] => 6/820460 [patent_app_country] => US [patent_app_date] => 1986-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4919 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/851/04851987.pdf [firstpage_image] =>[orig_patent_app_number] => 820460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2400638 [patent_doc_number] => 04782462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-01 [patent_title] => 'Raster scan video controller with programmable prioritized sharing of display memory between update and display processes and programmable memory access termination' [patent_app_type] => 1 [patent_app_number] => 6/815363 [patent_app_country] => US [patent_app_date] => 1985-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3884 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/782/04782462.pdf [firstpage_image] =>[orig_patent_app_number] => 815363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2452929 [patent_doc_number] => 04740916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-26 [patent_title] => 'Reconfigurable contiguous address space memory system including serially connected variable capacity memory modules and a split address bus' [patent_app_type] => 1 [patent_app_number] => 6/810622 [patent_app_country] => US [patent_app_date] => 1985-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2634 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/740/04740916.pdf [firstpage_image] =>[orig_patent_app_number] => 810622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2664019 [patent_doc_number] => 04962451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-09 [patent_title] => 'Cache-effective sort string generation method' [patent_app_type] => 1 [patent_app_number] => 6/796034 [patent_app_country] => US [patent_app_date] => 1985-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5285 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/962/04962451.pdf [firstpage_image] =>[orig_patent_app_number] => 796034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2431585 [patent_doc_number] => 04763245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-09 [patent_title] => 'Branch prediction mechanism in which a branch history table is updated using an operand sensitive branch table' [patent_app_type] => 1 [patent_app_number] => 6/793057 [patent_app_country] => US [patent_app_date] => 1985-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6318 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/763/04763245.pdf [firstpage_image] =>[orig_patent_app_number] => 793057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2716844 [patent_doc_number] => 04982361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-01 [patent_title] => 'Multiple loop parallel pipelined logic simulation system' [patent_app_type] => 1 [patent_app_number] => 6/789832 [patent_app_country] => US [patent_app_date] => 1985-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1977 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 442 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/982/04982361.pdf [firstpage_image] =>[orig_patent_app_number] => 789832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2450703 [patent_doc_number] => 04792893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-20 [patent_title] => 'Selectively recursive pipelined parallel vector logical operation system' [patent_app_type] => 1 [patent_app_number] => 6/782534 [patent_app_country] => US [patent_app_date] => 1985-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3940 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/792/04792893.pdf [firstpage_image] =>[orig_patent_app_number] => 782534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2396888 [patent_doc_number] => 04794523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-27 [patent_title] => 'Cache memory architecture for microcomputer speed-up board' [patent_app_type] => 1 [patent_app_number] => 6/782664 [patent_app_country] => US [patent_app_date] => 1985-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3509 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/794/04794523.pdf [firstpage_image] =>[orig_patent_app_number] => 782664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2431655 [patent_doc_number] => 04774653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-27 [patent_title] => 'Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers' [patent_app_type] => 1 [patent_app_number] => 6/763485 [patent_app_country] => US [patent_app_date] => 1985-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2103 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/774/04774653.pdf [firstpage_image] =>[orig_patent_app_number] => 763485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2537179 [patent_doc_number] => 04862346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-29 [patent_title] => 'Index for a register file with update of addresses using simultaneously received current, change, test, and reload addresses' [patent_app_type] => 1 [patent_app_number] => 6/751304 [patent_app_country] => US [patent_app_date] => 1985-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 11615 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/862/04862346.pdf [firstpage_image] =>[orig_patent_app_number] => 751304 [rel_patent_id] =>[rel_patent_doc_number] =>)