Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16559083 [patent_doc_number] => 20210004232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Energy Efficient Processor Core Architecture for Image Processor [patent_app_type] => utility [patent_app_number] => 17/001097 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001097
Energy efficient processor core architecture for image processor Aug 23, 2020 Issued
Array ( [id] => 17379893 [patent_doc_number] => 11237909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Load exploitation and improved pipelineability of hardware instructions [patent_app_type] => utility [patent_app_number] => 16/999887 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14808 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999887 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999887
Load exploitation and improved pipelineability of hardware instructions Aug 20, 2020 Issued
Array ( [id] => 17151240 [patent_doc_number] => 11144317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => AC parallelization circuit, AC parallelization method, and parallel information processing device [patent_app_type] => utility [patent_app_number] => 16/997992 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3626 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997992
AC parallelization circuit, AC parallelization method, and parallel information processing device Aug 19, 2020 Issued
Array ( [id] => 17151240 [patent_doc_number] => 11144317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => AC parallelization circuit, AC parallelization method, and parallel information processing device [patent_app_type] => utility [patent_app_number] => 16/997992 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3626 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997992
AC parallelization circuit, AC parallelization method, and parallel information processing device Aug 19, 2020 Issued
Array ( [id] => 17469235 [patent_doc_number] => 11275712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => SIMD controller and SIMD predication scheme [patent_app_type] => utility [patent_app_number] => 16/998186 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10024 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998186 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/998186
SIMD controller and SIMD predication scheme Aug 19, 2020 Issued
Array ( [id] => 17589493 [patent_doc_number] => 11327766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Instruction dispatch routing [patent_app_type] => utility [patent_app_number] => 16/945404 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11801 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945404 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945404
Instruction dispatch routing Jul 30, 2020 Issued
Array ( [id] => 17216386 [patent_doc_number] => 20210349724 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-11-11 [patent_title] => SECURING CONDITIONAL SPECULATIVE INSTRUCTION EXECUTION [patent_app_type] => utility [patent_app_number] => 16/942591 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942591
Securing conditional speculative instruction execution Jul 28, 2020 Issued
Array ( [id] => 17216386 [patent_doc_number] => 20210349724 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-11-11 [patent_title] => SECURING CONDITIONAL SPECULATIVE INSTRUCTION EXECUTION [patent_app_type] => utility [patent_app_number] => 16/942591 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942591
Securing conditional speculative instruction execution Jul 28, 2020 Issued
Array ( [id] => 17394891 [patent_doc_number] => 11243905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-08 [patent_title] => RISC processor having specialized data path for specialized registers [patent_app_type] => utility [patent_app_number] => 16/941485 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941485
RISC processor having specialized data path for specialized registers Jul 27, 2020 Issued
Array ( [id] => 17106371 [patent_doc_number] => 11126588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => RISC processor having specialized registers [patent_app_type] => utility [patent_app_number] => 16/941499 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 11337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941499
RISC processor having specialized registers Jul 27, 2020 Issued
Array ( [id] => 17151242 [patent_doc_number] => 11144319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Redistribution of architected states for a processor register file [patent_app_type] => utility [patent_app_number] => 16/940433 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940433
Redistribution of architected states for a processor register file Jul 27, 2020 Issued
Array ( [id] => 17372105 [patent_doc_number] => 20220027157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => VALIDATING MACHINE-READABLE INSTRUCTIONS USING AN ITERATIVE VALIDATION PROCESS [patent_app_type] => utility [patent_app_number] => 16/937048 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937048
Validating machine-readable instructions using an iterative validation process Jul 22, 2020 Issued
Array ( [id] => 17331388 [patent_doc_number] => 11221851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Method executed by computing device, apparatus, device and computer-readable storage medium [patent_app_type] => utility [patent_app_number] => 16/936676 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936676 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936676
Method executed by computing device, apparatus, device and computer-readable storage medium Jul 22, 2020 Issued
Array ( [id] => 17358646 [patent_doc_number] => 20220019442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => RECONFIGURABLE PROCESSING-IN-MEMORY LOGIC USING LOOK-UP TABLES [patent_app_type] => utility [patent_app_number] => 16/932524 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932524
Reconfigurable processing-in-memory logic using look-up tables Jul 16, 2020 Issued
Array ( [id] => 16584880 [patent_doc_number] => 20210019282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => Packet Transmission Method and Apparatus [patent_app_type] => utility [patent_app_number] => 16/928396 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928396
Packet transmission method and apparatus Jul 13, 2020 Issued
Array ( [id] => 18539373 [patent_doc_number] => 20230244481 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2023-08-03 [patent_title] => BLOCKCHAIN MICROPROCESSOR AND METHOD [patent_app_type] => utility [patent_app_number] => 17/626111 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/626111
BLOCKCHAIN MICROPROCESSOR AND METHOD Jul 9, 2020 Abandoned
Array ( [id] => 18539373 [patent_doc_number] => 20230244481 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2023-08-03 [patent_title] => BLOCKCHAIN MICROPROCESSOR AND METHOD [patent_app_type] => utility [patent_app_number] => 17/626111 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/626111
BLOCKCHAIN MICROPROCESSOR AND METHOD Jul 9, 2020 Abandoned
Array ( [id] => 17365041 [patent_doc_number] => 11232062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-25 [patent_title] => Parallelism within a systolic array using multiple accumulate busses [patent_app_type] => utility [patent_app_number] => 16/915783 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915783
Parallelism within a systolic array using multiple accumulate busses Jun 28, 2020 Issued
Array ( [id] => 17542903 [patent_doc_number] => 11308026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Multiple busses interleaved in a systolic array [patent_app_type] => utility [patent_app_number] => 16/915777 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36447 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915777
Multiple busses interleaved in a systolic array Jun 28, 2020 Issued
Array ( [id] => 17542904 [patent_doc_number] => 11308027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Multiple accumulate busses in a systolic array [patent_app_type] => utility [patent_app_number] => 16/915795 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915795
Multiple accumulate busses in a systolic array Jun 28, 2020 Issued
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