Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17076833 [patent_doc_number] => 11113233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Multiple busses in a grouped systolic array [patent_app_type] => utility [patent_app_number] => 16/915828 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36446 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915828
Multiple busses in a grouped systolic array Jun 28, 2020 Issued
Array ( [id] => 17771161 [patent_doc_number] => 11403102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Technology to learn and offload common patterns of memory access and computation [patent_app_type] => utility [patent_app_number] => 16/914293 [patent_app_country] => US [patent_app_date] => 2020-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9950 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914293
Technology to learn and offload common patterns of memory access and computation Jun 26, 2020 Issued
Array ( [id] => 17437957 [patent_doc_number] => 11263291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Systems and methods for combining low-mantissa units to achieve and exceed FP64 emulation of matrix multiplication [patent_app_type] => utility [patent_app_number] => 16/913911 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 15577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913911
Systems and methods for combining low-mantissa units to achieve and exceed FP64 emulation of matrix multiplication Jun 25, 2020 Issued
Array ( [id] => 17288427 [patent_doc_number] => 11204977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs [patent_app_type] => utility [patent_app_number] => 16/913800 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 29774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913800
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs Jun 25, 2020 Issued
Array ( [id] => 16543287 [patent_doc_number] => 20200409702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => CALCULATION ENGINE FOR PERFORMING CALCULATIONS BASED ON DEPENDENCIES IN A SELF-DESCRIBING DATA SYSTEM [patent_app_type] => utility [patent_app_number] => 16/913537 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913537
Calculation engine for performing calculations based on dependencies in a self-describing data system Jun 25, 2020 Issued
Array ( [id] => 17106473 [patent_doc_number] => 11126691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => Apparatus and method for generating a vector of elements with a wrapping constraint [patent_app_type] => utility [patent_app_number] => 16/909147 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 14 [patent_no_of_words] => 12974 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909147
Apparatus and method for generating a vector of elements with a wrapping constraint Jun 22, 2020 Issued
Array ( [id] => 17925052 [patent_doc_number] => 11468306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Storage device with artificial intelligence and storage system including the same [patent_app_type] => utility [patent_app_number] => 16/906209 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906209
Storage device with artificial intelligence and storage system including the same Jun 18, 2020 Issued
Array ( [id] => 17245658 [patent_doc_number] => 20210365402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING MACHINES USING SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 16/900236 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900236
Computing efficient cross channel operations in parallel computing machines using systolic arrays Jun 11, 2020 Issued
Array ( [id] => 18015516 [patent_doc_number] => 11507814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-22 [patent_title] => Neural network based on total hamming distance [patent_app_type] => utility [patent_app_number] => 16/899806 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899806
Neural network based on total hamming distance Jun 11, 2020 Issued
Array ( [id] => 17707397 [patent_doc_number] => 20220207404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => INPUT/OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES [patent_app_type] => utility [patent_app_number] => 17/607278 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17607278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/607278
Input/output systems and methods for superconducting devices Jun 10, 2020 Issued
Array ( [id] => 17763376 [patent_doc_number] => 20220236988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => MASK OPERATION METHOD FOR EXPLICIT INDEPENDENT MASK REGISTER IN GPU [patent_app_type] => utility [patent_app_number] => 17/618506 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17618506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/618506
Mask operation method for explicit independent mask register in GPU Jun 10, 2020 Issued
Array ( [id] => 17165367 [patent_doc_number] => 11151470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Pre-screening and tuning heterojunctions for topological quantum computer [patent_app_type] => utility [patent_app_number] => 16/886670 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886670
Pre-screening and tuning heterojunctions for topological quantum computer May 27, 2020 Issued
Array ( [id] => 17379815 [patent_doc_number] => 11237831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Method and apparatus for permuting streamed data elements [patent_app_type] => utility [patent_app_number] => 16/878611 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 61 [patent_no_of_words] => 38484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878611 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878611
Method and apparatus for permuting streamed data elements May 19, 2020 Issued
Array ( [id] => 16470248 [patent_doc_number] => 20200371785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => COMPUTING DEVICE AND NEURAL NETWORK PROCESSOR INCORPORATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/876133 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876133 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876133
Computing device and neural network processor incorporating the same May 17, 2020 Issued
Array ( [id] => 17009636 [patent_doc_number] => 20210240797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => ACCELERATOR FOR DENSE AND SPARSE MATRIX COMPUTATIONS [patent_app_type] => utility [patent_app_number] => 16/862370 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/862370
Accelerator for dense and sparse matrix computations Apr 28, 2020 Issued
Array ( [id] => 17187249 [patent_doc_number] => 20210334134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => Handling Multiple Graphs, Contexts and Programs in a Coarse-Grain Reconfigurable Array Processor [patent_app_type] => utility [patent_app_number] => 16/860070 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860070
Handling multiple graphs, contexts and programs in a coarse-grain reconfigurable array processor Apr 27, 2020 Issued
Array ( [id] => 16780682 [patent_doc_number] => 20210117761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD AND APPARATUS WITH DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 16/857740 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16857740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/857740
Method and apparatus with data processing Apr 23, 2020 Issued
Array ( [id] => 17364914 [patent_doc_number] => 11231935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Vectorized sorted-set intersection using conflict-detection SIMD instructions [patent_app_type] => utility [patent_app_number] => 16/846773 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846773
Vectorized sorted-set intersection using conflict-detection SIMD instructions Apr 12, 2020 Issued
Array ( [id] => 17379817 [patent_doc_number] => 11237833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Multiply-accumulate instruction processing method and apparatus [patent_app_type] => utility [patent_app_number] => 16/845606 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10076 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845606 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845606
Multiply-accumulate instruction processing method and apparatus Apr 9, 2020 Issued
Array ( [id] => 17091584 [patent_doc_number] => 11119773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-14 [patent_title] => Runtime quantum-memory management [patent_app_type] => utility [patent_app_number] => 16/844948 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844948
Runtime quantum-memory management Apr 8, 2020 Issued
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