Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16903151 [patent_doc_number] => 20210182067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO MULTIPLY FLOATING-POINT VALUES OF ABOUT ONE [patent_app_type] => utility [patent_app_number] => 16/714656 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714656
Apparatuses, methods, and systems for instructions to multiply floating-point values of about one Dec 12, 2019 Issued
Array ( [id] => 18087722 [patent_doc_number] => 11537859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Flexible precision neural inference processing unit [patent_app_type] => utility [patent_app_number] => 16/705565 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705565
Flexible precision neural inference processing unit Dec 5, 2019 Issued
Array ( [id] => 16077377 [patent_doc_number] => 20200192675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => MEMRISTOR BASED MULTITHREADING [patent_app_type] => utility [patent_app_number] => 16/699184 [patent_app_country] => US [patent_app_date] => 2019-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699184 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699184
MEMRISTOR BASED MULTITHREADING Nov 28, 2019 Abandoned
Array ( [id] => 17925050 [patent_doc_number] => 11468304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-11 [patent_title] => Synchronizing operations in hardware accelerator [patent_app_type] => utility [patent_app_number] => 16/696377 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696377
Synchronizing operations in hardware accelerator Nov 25, 2019 Issued
Array ( [id] => 17940825 [patent_doc_number] => 11475283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Multi dimensional convolution in neural network processor [patent_app_type] => utility [patent_app_number] => 16/662789 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11427 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662789
Multi dimensional convolution in neural network processor Oct 23, 2019 Issued
Array ( [id] => 18781307 [patent_doc_number] => 11823052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Configurable MAC for neural network applications [patent_app_type] => utility [patent_app_number] => 16/599306 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7088 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599306
Configurable MAC for neural network applications Oct 10, 2019 Issued
Array ( [id] => 15439919 [patent_doc_number] => 20200034143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => TECHNIQUES FOR COMPREHENSIVELY SYNCHRONIZING EXECUTION THREADS [patent_app_type] => utility [patent_app_number] => 16/595398 [patent_app_country] => US [patent_app_date] => 2019-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16595398 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/595398
Techniques for comprehensively synchronizing execution threads Oct 6, 2019 Issued
Array ( [id] => 15854517 [patent_doc_number] => 10642541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 16/590999 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7021 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/590999
Machine perception and dense algorithm integrated circuit Oct 1, 2019 Issued
Array ( [id] => 18837392 [patent_doc_number] => 11845452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Electronic control device and parallel processing method [patent_app_type] => utility [patent_app_number] => 17/282687 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10592 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17282687 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/282687
Electronic control device and parallel processing method Sep 30, 2019 Issued
Array ( [id] => 16470254 [patent_doc_number] => 20200371791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => METHOD AND APPARATUS FOR VECTOR SORTING [patent_app_type] => utility [patent_app_number] => 16/589118 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589118 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589118
Method and apparatus for vector sorting Sep 29, 2019 Issued
Array ( [id] => 16729720 [patent_doc_number] => 20210096867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => Instruction Length Decoder System and Method [patent_app_type] => utility [patent_app_number] => 16/586715 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586715 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586715
Instruction length decoder system and method Sep 26, 2019 Issued
Array ( [id] => 15412393 [patent_doc_number] => 20200026519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => PROCESSOR TRACE EXTENSIONS TO FACILITATE REAL-TIME SECURITY MONITORING [patent_app_type] => utility [patent_app_number] => 16/585287 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585287
Processor trace extensions to facilitate real-time security monitoring Sep 26, 2019 Issued
Array ( [id] => 15412381 [patent_doc_number] => 20200026513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => TECHNIQUES FOR DECOUPLED ACCESS-EXECUTE NEAR-MEMORY PROCESSING [patent_app_type] => utility [patent_app_number] => 16/585521 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585521 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585521
Techniques for decoupled access-execute near-memory processing Sep 26, 2019 Issued
Array ( [id] => 16722161 [patent_doc_number] => 20210089308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SYSTEMS AND METHODS FOR PROCESSING INSTRUCTIONS HAVING WIDE IMMEDIATE OPERANDS [patent_app_type] => utility [patent_app_number] => 16/579161 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579161 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/579161
Systems and methods for processing instructions having wide immediate operands Sep 22, 2019 Issued
Array ( [id] => 16651955 [patent_doc_number] => 10929132 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications [patent_app_type] => utility [patent_app_number] => 16/579806 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 15921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/579806
Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications Sep 22, 2019 Issued
Array ( [id] => 18000037 [patent_doc_number] => 11501145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Memory operation for systolic array [patent_app_type] => utility [patent_app_number] => 16/573201 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573201
Memory operation for systolic array Sep 16, 2019 Issued
Array ( [id] => 16714622 [patent_doc_number] => 20210081769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => Performance Estimation-Based Resource Allocation for Reconfigurable Architectures [patent_app_type] => utility [patent_app_number] => 16/572527 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/572527
Performance estimation-based resource allocation for reconfigurable architectures Sep 15, 2019 Issued
Array ( [id] => 15297349 [patent_doc_number] => 20190391810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => LOW LATENCY EXECUTION OF FLOATING-POINT RECORD FORM INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/562077 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562077
Low latency execution of floating-point record form instructions Sep 4, 2019 Issued
Array ( [id] => 16208889 [patent_doc_number] => 20200241879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS [patent_app_type] => utility [patent_app_number] => 16/560895 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560895
Issuing instructions to multiple execution units Sep 3, 2019 Issued
Array ( [id] => 15685253 [patent_doc_number] => 20200097290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX AND AN IMMEDIATE [patent_app_type] => utility [patent_app_number] => 16/560223 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560223
METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX AND AN IMMEDIATE Sep 3, 2019 Abandoned
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