Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15297389 [patent_doc_number] => 20190391830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => SYSTEM AND METHOD OF EMULATING EXECUTION OF FILES BASED ON EMULATION TIME [patent_app_type] => utility [patent_app_number] => 16/558491 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558491 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558491
System and method of emulating execution of files based on emulation time Sep 2, 2019 Issued
Array ( [id] => 18204489 [patent_doc_number] => 11586886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Neural network apparatus and method with bitwise operation [patent_app_type] => utility [patent_app_number] => 16/542803 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 12530 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542803 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542803
Neural network apparatus and method with bitwise operation Aug 15, 2019 Issued
Array ( [id] => 17651432 [patent_doc_number] => 11354159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Method, a device, and a computer program product for determining a resource required for executing a code segment [patent_app_type] => utility [patent_app_number] => 16/540385 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540385 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540385
Method, a device, and a computer program product for determining a resource required for executing a code segment Aug 13, 2019 Issued
Array ( [id] => 16833912 [patent_doc_number] => 11010163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Hierarchical general register file (GRF) for execution block [patent_app_type] => utility [patent_app_number] => 16/526147 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 36 [patent_no_of_words] => 27386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526147
Hierarchical general register file (GRF) for execution block Jul 29, 2019 Issued
Array ( [id] => 16600105 [patent_doc_number] => 20210026636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => PERFORMING ATOMIC STORE-AND-INVALIDATE OPERATIONS IN PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 16/522755 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522755
Performing atomic store-and-invalidate operations in processor-based devices Jul 25, 2019 Issued
Array ( [id] => 16758494 [patent_doc_number] => 10977042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Using expedited RCU grace periods to avoid out-of-memory conditions for offloaded RCU callbacks [patent_app_type] => utility [patent_app_number] => 16/523489 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523489 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523489
Using expedited RCU grace periods to avoid out-of-memory conditions for offloaded RCU callbacks Jul 25, 2019 Issued
Array ( [id] => 16698652 [patent_doc_number] => 10949249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Task processor [patent_app_type] => utility [patent_app_number] => 16/458618 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 22662 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458618
Task processor Jun 30, 2019 Issued
Array ( [id] => 16879808 [patent_doc_number] => 11029955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Instruction and logic for processing text strings [patent_app_type] => utility [patent_app_number] => 16/458014 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11665 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458014 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458014
Instruction and logic for processing text strings Jun 28, 2019 Issued
Array ( [id] => 16864496 [patent_doc_number] => 11023236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Instruction and logic for processing text strings [patent_app_type] => utility [patent_app_number] => 16/458012 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11664 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458012 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458012
Instruction and logic for processing text strings Jun 28, 2019 Issued
Array ( [id] => 16543249 [patent_doc_number] => 20200409664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => TRANSPOSE OPERATIONS USING PROCESSING ELEMENT ARRAY [patent_app_type] => utility [patent_app_number] => 16/455201 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/455201
Transpose operations using processing element array Jun 26, 2019 Issued
Array ( [id] => 16879806 [patent_doc_number] => 11029953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Branch prediction unit in service of short microcode flows [patent_app_type] => utility [patent_app_number] => 16/453704 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 16516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453704 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453704
Branch prediction unit in service of short microcode flows Jun 25, 2019 Issued
Array ( [id] => 16543622 [patent_doc_number] => 20200410037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => VECTOR MATRIX MULTIPLICATION WITH 3D NAND [patent_app_type] => utility [patent_app_number] => 16/452418 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452418 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452418
Vector matrix multiplication with 3D NAND Jun 24, 2019 Issued
Array ( [id] => 16780418 [patent_doc_number] => 20210117497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION [patent_app_type] => utility [patent_app_number] => 17/251720 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17251720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/251720
Digital signal processor and method of operation Jun 18, 2019 Issued
Array ( [id] => 18303678 [patent_doc_number] => 11625584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Reconfigurable memory compression techniques for deep neural networks [patent_app_type] => utility [patent_app_number] => 16/443548 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9201 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443548 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443548
Reconfigurable memory compression techniques for deep neural networks Jun 16, 2019 Issued
Array ( [id] => 15106147 [patent_doc_number] => 10474398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 16/439988 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7008 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16439988 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/439988
Machine perception and dense algorithm integrated circuit Jun 12, 2019 Issued
Array ( [id] => 16508126 [patent_doc_number] => 20200387382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => MECHANISM FOR INSTRUCTION FUSION USING TAGS [patent_app_type] => utility [patent_app_number] => 16/434134 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16434134 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/434134
Mechanism for instruction fusion using tags Jun 5, 2019 Issued
Array ( [id] => 16508122 [patent_doc_number] => 20200387378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => ACCOUNTING FOR MULTIPLE PIPELINE DEPTHS IN PROCESSOR INSTRUMENTATION [patent_app_type] => utility [patent_app_number] => 16/433381 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16433381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/433381
Accounting for multiple pipeline depths in processor instrumentation Jun 5, 2019 Issued
Array ( [id] => 16508124 [patent_doc_number] => 20200387380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => APPARATUS AND METHOD FOR MAKING PREDICTIONS FOR BRANCH INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/431881 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431881 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431881
Apparatus and method for making predictions for branch instructions Jun 4, 2019 Issued
Array ( [id] => 16683411 [patent_doc_number] => 10942890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Bit string accumulation in memory array periphery [patent_app_type] => utility [patent_app_number] => 16/430737 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 23561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430737 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430737
Bit string accumulation in memory array periphery Jun 3, 2019 Issued
Array ( [id] => 16683410 [patent_doc_number] => 10942889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Bit string accumulation in memory array periphery [patent_app_type] => utility [patent_app_number] => 16/430689 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 22321 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430689
Bit string accumulation in memory array periphery Jun 3, 2019 Issued
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