
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20070651
[patent_doc_number] => 20250208873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => HIGH LEVEL GRAPH COMPUTING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/663946
[patent_app_country] => US
[patent_app_date] => 2024-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663946
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/663946 | HIGH LEVEL GRAPH COMPUTING SYSTEM | May 13, 2024 | Pending |
Array
(
[id] => 20070651
[patent_doc_number] => 20250208873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => HIGH LEVEL GRAPH COMPUTING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/663946
[patent_app_country] => US
[patent_app_date] => 2024-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663946
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/663946 | HIGH LEVEL GRAPH COMPUTING SYSTEM | May 13, 2024 | Pending |
Array
(
[id] => 20070651
[patent_doc_number] => 20250208873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => HIGH LEVEL GRAPH COMPUTING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/663946
[patent_app_country] => US
[patent_app_date] => 2024-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663946
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/663946 | HIGH LEVEL GRAPH COMPUTING SYSTEM | May 13, 2024 | Pending |
Array
(
[id] => 20351459
[patent_doc_number] => 20250348311
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-13
[patent_title] => VECTOR PROCESSOR TILE ARRAY WITH INPUT AND OUTPUT STREAMS
[patent_app_type] => utility
[patent_app_number] => 18/662955
[patent_app_country] => US
[patent_app_date] => 2024-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4236
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662955
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/662955 | VECTOR PROCESSOR TILE ARRAY WITH INPUT AND OUTPUT STREAMS | May 12, 2024 | Pending |
Array
(
[id] => 20351468
[patent_doc_number] => 20250348320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-13
[patent_title] => COMPUTING DEVICES WITH INSTRUCTION QUEUES AND PROCESSING-ELEMENT ARRAY CONTROLLERS
[patent_app_type] => utility
[patent_app_number] => 18/661145
[patent_app_country] => US
[patent_app_date] => 2024-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661145
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/661145 | COMPUTING DEVICES WITH INSTRUCTION QUEUES AND PROCESSING-ELEMENT ARRAY CONTROLLERS | May 9, 2024 | Pending |
Array
(
[id] => 20351468
[patent_doc_number] => 20250348320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-13
[patent_title] => COMPUTING DEVICES WITH INSTRUCTION QUEUES AND PROCESSING-ELEMENT ARRAY CONTROLLERS
[patent_app_type] => utility
[patent_app_number] => 18/661145
[patent_app_country] => US
[patent_app_date] => 2024-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661145
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/661145 | COMPUTING DEVICES WITH INSTRUCTION QUEUES AND PROCESSING-ELEMENT ARRAY CONTROLLERS | May 9, 2024 | Pending |
Array
(
[id] => 19603181
[patent_doc_number] => 20240394061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => METHODS AND SYSTEMS FOR DATA TRANSFER
[patent_app_type] => utility
[patent_app_number] => 18/660683
[patent_app_country] => US
[patent_app_date] => 2024-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9840
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660683
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/660683 | METHODS AND SYSTEMS FOR DATA TRANSFER | May 9, 2024 | Pending |
Array
(
[id] => 20388177
[patent_doc_number] => 12487903
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-02
[patent_title] => Automatic generation of computation kernels for approximating elementary functions
[patent_app_type] => utility
[patent_app_number] => 18/652846
[patent_app_country] => US
[patent_app_date] => 2024-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5399
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652846
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/652846 | Automatic generation of computation kernels for approximating elementary functions | May 1, 2024 | Issued |
Array
(
[id] => 20388177
[patent_doc_number] => 12487903
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-02
[patent_title] => Automatic generation of computation kernels for approximating elementary functions
[patent_app_type] => utility
[patent_app_number] => 18/652846
[patent_app_country] => US
[patent_app_date] => 2024-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5399
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652846
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/652846 | Automatic generation of computation kernels for approximating elementary functions | May 1, 2024 | Issued |
Array
(
[id] => 19383063
[patent_doc_number] => 20240272933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => SYSTEM AND METHOD TO ACCELERATE REDUCE OPERATIONS IN GRAPHICS PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 18/626689
[patent_app_country] => US
[patent_app_date] => 2024-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16334
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626689
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/626689 | System and method to accelerate reduce operations in graphics processor | Apr 3, 2024 | Issued |
Array
(
[id] => 19451204
[patent_doc_number] => 20240311334
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => Methods and Circuits for Streaming Data to Processing Elements in Stacked Processor-Plus-Memory Architecture
[patent_app_type] => utility
[patent_app_number] => 18/624877
[patent_app_country] => US
[patent_app_date] => 2024-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4792
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624877
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/624877 | Methods and Circuits for Streaming Data to Processing Elements in Stacked Processor-Plus-Memory Architecture | Apr 1, 2024 | Pending |
Array
(
[id] => 20203008
[patent_doc_number] => 12405787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-02
[patent_title] => Utilizing structured sparsity in systolic arrays
[patent_app_type] => utility
[patent_app_number] => 18/621539
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 9338
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621539
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/621539 | Utilizing structured sparsity in systolic arrays | Mar 28, 2024 | Issued |
Array
(
[id] => 20203008
[patent_doc_number] => 12405787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-02
[patent_title] => Utilizing structured sparsity in systolic arrays
[patent_app_type] => utility
[patent_app_number] => 18/621539
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 9338
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621539
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/621539 | Utilizing structured sparsity in systolic arrays | Mar 28, 2024 | Issued |
Array
(
[id] => 19320178
[patent_doc_number] => 20240241722
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 18/619570
[patent_app_country] => US
[patent_app_date] => 2024-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27046
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619570
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/619570 | APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS | Mar 27, 2024 | Abandoned |
Array
(
[id] => 20249747
[patent_doc_number] => 20250298616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => COMPARE COMMAND
[patent_app_type] => utility
[patent_app_number] => 18/609081
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6010
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609081
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609081 | COMPARE COMMAND | Mar 18, 2024 | Pending |
Array
(
[id] => 20440292
[patent_doc_number] => 12511128
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Reconfigurable processing-in-memory logic using look-up tables
[patent_app_type] => utility
[patent_app_number] => 18/606142
[patent_app_country] => US
[patent_app_date] => 2024-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2269
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606142
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/606142 | Reconfigurable processing-in-memory logic using look-up tables | Mar 14, 2024 | Issued |
Array
(
[id] => 20440292
[patent_doc_number] => 12511128
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Reconfigurable processing-in-memory logic using look-up tables
[patent_app_type] => utility
[patent_app_number] => 18/606142
[patent_app_country] => US
[patent_app_date] => 2024-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2269
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606142
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/606142 | Reconfigurable processing-in-memory logic using look-up tables | Mar 14, 2024 | Issued |
Array
(
[id] => 20415794
[patent_doc_number] => 12499080
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-16
[patent_title] => Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures
[patent_app_type] => utility
[patent_app_number] => 18/606924
[patent_app_country] => US
[patent_app_date] => 2024-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10834
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606924
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/606924 | Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures | Mar 14, 2024 | Issued |
Array
(
[id] => 20415794
[patent_doc_number] => 12499080
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-16
[patent_title] => Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures
[patent_app_type] => utility
[patent_app_number] => 18/606924
[patent_app_country] => US
[patent_app_date] => 2024-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10834
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606924
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/606924 | Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures | Mar 14, 2024 | Issued |
Array
(
[id] => 20234275
[patent_doc_number] => 20250291594
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-18
[patent_title] => FUSED COMPARISON ADD INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 18/606865
[patent_app_country] => US
[patent_app_date] => 2024-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1098
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606865
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/606865 | FUSED COMPARISON ADD INSTRUCTIONS | Mar 14, 2024 | Pending |