Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16470169 [patent_doc_number] => 20200371706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => QUICK CLEARING OF REGISTERS [patent_app_type] => utility [patent_app_number] => 16/422522 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422522 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422522
Quick clearing of registers May 23, 2019 Issued
Array ( [id] => 16470791 [patent_doc_number] => 20200372328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => ACCELERATING NEURON COMPUTATIONS IN ARTIFICIAL NEURAL NETWORKS WITH DUAL SPARSITY [patent_app_type] => utility [patent_app_number] => 16/416891 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416891 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416891
Accelerating neuron computations in artificial neural networks with dual sparsity May 19, 2019 Issued
Array ( [id] => 17636787 [patent_doc_number] => 11347511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Floating-point scaling operation [patent_app_type] => utility [patent_app_number] => 16/416453 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 14569 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416453
Floating-point scaling operation May 19, 2019 Issued
Array ( [id] => 16972297 [patent_doc_number] => 11068269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-20 [patent_title] => Instruction decoding using hash tables [patent_app_type] => utility [patent_app_number] => 16/417033 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7243 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417033
Instruction decoding using hash tables May 19, 2019 Issued
Array ( [id] => 14840711 [patent_doc_number] => 20190278756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SORTING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/414301 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414301 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414301
Sorting system May 15, 2019 Issued
Array ( [id] => 16307334 [patent_doc_number] => 10776126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-15 [patent_title] => Flexible hardware engines for handling operating on multidimensional vectors in a video processor [patent_app_type] => utility [patent_app_number] => 16/397476 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397476 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397476
Flexible hardware engines for handling operating on multidimensional vectors in a video processor Apr 28, 2019 Issued
Array ( [id] => 14750615 [patent_doc_number] => 20190258481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => INTERRUPTIBLE AND RESTARTABLE MATRIX MULTIPLICATION INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/398200 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16398200 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/398200
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems Apr 28, 2019 Issued
Array ( [id] => 17238278 [patent_doc_number] => 11182157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Information processing device, arithmetic device, and information processing method [patent_app_type] => utility [patent_app_number] => 17/047776 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7205 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17047776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/047776
Information processing device, arithmetic device, and information processing method Apr 25, 2019 Issued
Array ( [id] => 16667076 [patent_doc_number] => 10936322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Method for handling exceptions in exception-driven system [patent_app_type] => utility [patent_app_number] => 16/392408 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16392408 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/392408
Method for handling exceptions in exception-driven system Apr 22, 2019 Issued
Array ( [id] => 16856841 [patent_doc_number] => 20210157586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => METHOD SECURED AGAINST SIDE-CHANNEL ATTACKS PERFORMING AN ARITHMETIC OPERATION OF A CRYPTOGRAPHIC ALGORITHM MIXING BOOLEAN AND ARITHMETIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/048262 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17048262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/048262
Method secured against side-channel attacks performing an arithmetic operation of a cryptographic algorithm mixing Boolean and arithmetic operations Apr 15, 2019 Issued
Array ( [id] => 16651954 [patent_doc_number] => 10929131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Instruction and logic for processing text strings [patent_app_type] => utility [patent_app_number] => 16/384865 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11630 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384865 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384865
Instruction and logic for processing text strings Apr 14, 2019 Issued
Array ( [id] => 14657471 [patent_doc_number] => 20190235864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => GENERATING AND VERIFYING HARDWARE INSTRUCTION TRACES INCLUDING MEMORY DATA CONTENTS [patent_app_type] => utility [patent_app_number] => 16/382740 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382740
Generating and verifying hardware instruction traces including memory data contents Apr 11, 2019 Issued
Array ( [id] => 16363911 [patent_doc_number] => 20200320662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => ACCUMULATOR POOLING MECHANISM [patent_app_type] => utility [patent_app_number] => 16/378047 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378047 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378047
Accumulator pooling mechanism Apr 7, 2019 Issued
Array ( [id] => 14585347 [patent_doc_number] => 20190220282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Energy Efficient Processor Core Architecture for Image Processor [patent_app_type] => utility [patent_app_number] => 16/368288 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368288
Energy efficient processor core architecture for image processor Mar 27, 2019 Issued
Array ( [id] => 16346870 [patent_doc_number] => 20200311521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => LOOP-BASED EXECUTION FOR EFFICIENT DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 16/365460 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16365460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/365460
LOOP-BASED EXECUTION FOR EFFICIENT DEEP LEARNING Mar 25, 2019 Abandoned
Array ( [id] => 17955503 [patent_doc_number] => 11481612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Storage of input values across multiple cores of neural network inference circuit [patent_app_type] => utility [patent_app_number] => 16/355656 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 27154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/355656
Storage of input values across multiple cores of neural network inference circuit Mar 14, 2019 Issued
Array ( [id] => 16371072 [patent_doc_number] => 10802830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Imprecise register dependency tracking [patent_app_type] => utility [patent_app_number] => 16/292933 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292933
Imprecise register dependency tracking Mar 4, 2019 Issued
Array ( [id] => 16535164 [patent_doc_number] => 10877764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Vector processor, operation performing method, and non-transitory computer-readable recording medium for recording program [patent_app_type] => utility [patent_app_number] => 16/292554 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9282 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292554
Vector processor, operation performing method, and non-transitory computer-readable recording medium for recording program Mar 4, 2019 Issued
Array ( [id] => 16651964 [patent_doc_number] => 10929141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Selective use of taint protection during speculative execution [patent_app_type] => utility [patent_app_number] => 16/293266 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8153 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16293266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/293266
Selective use of taint protection during speculative execution Mar 4, 2019 Issued
Array ( [id] => 16706225 [patent_doc_number] => 10956157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Taint protection during speculative execution [patent_app_type] => utility [patent_app_number] => 16/293154 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7586 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16293154 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/293154
Taint protection during speculative execution Mar 4, 2019 Issued
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