Eliseo Ramos Feliciano

Array ( [id] => 14642233 [patent_doc_number] => 10365860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-30 [patent_title] => Machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 16/290064 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6992 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16290064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16764174 [patent_doc_number] => 20210109755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => BRANCH TARGET VARIANT OF BRANCH-WITH-LINK INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/971755 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16971755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18291283 [patent_doc_number] => 11620153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Instruction interrupt suppression of overflow exception [patent_app_type] => utility [patent_app_number] => 16/266752 [patent_app_country] => US [patent_app_date] => 2019-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7607 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16574116 [patent_doc_number] => 10896039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Programmable matrix processing engine [patent_app_type] => utility [patent_app_number] => 16/264483 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14836 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16264483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16566184 [patent_doc_number] => 10891554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Quantum processor with instance programmable qubit connectivity [patent_app_type] => utility [patent_app_number] => 16/258082 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 20856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16258082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16651956 [patent_doc_number] => 10929133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Apparatuses, methods, and systems for element sorting of vectors [patent_app_type] => utility [patent_app_number] => 16/249870 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 20949 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14379133 [patent_doc_number] => 20190163479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => INDIRECT TARGET TAGGED GEOMETRIC BRANCH PREDICTION USING A SET OF TARGET ADDRESS PATTERN DATA [patent_app_type] => utility [patent_app_number] => 16/247714 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14570797 [patent_doc_number] => 20190213005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => NEURAL NETWORK COMPUTE TILE [patent_app_type] => utility [patent_app_number] => 16/239760 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16494279 [patent_doc_number] => 10860321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Electronic device and method for processing instruction using the same [patent_app_type] => utility [patent_app_number] => 16/205297 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8027 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14585341 [patent_doc_number] => 20190220279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => SIMULATION OF EXCLUSIVE INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/203886 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16416542 [patent_doc_number] => 10824434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-03 [patent_title] => Dynamically structured single instruction, multiple data (SIMD) instructions [patent_app_type] => utility [patent_app_number] => 16/204991 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 16322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16706428 [patent_doc_number] => 10956361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Processor core design optimized for machine learning applications [patent_app_type] => utility [patent_app_number] => 16/205211 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16706232 [patent_doc_number] => 10956164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Gating updates to branch predictors to reduce pollution from infrequently executed branches [patent_app_type] => utility [patent_app_number] => 16/201132 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7724 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14379163 [patent_doc_number] => 20190163494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => PROCESSOR AND PIPELINING METHOD [patent_app_type] => utility [patent_app_number] => 16/201296 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15966825 [patent_doc_number] => 20200167164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => LOOP EXIT PREDICTOR [patent_app_type] => utility [patent_app_number] => 16/200491 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16363134 [patent_doc_number] => 20200319885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => VECTOR ADD-WITH-CARRY INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/650999 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16650999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18174457 [patent_doc_number] => 11574171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Neural network architecture using convolution engines [patent_app_type] => utility [patent_app_number] => 16/181559 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 17472 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13992051 [patent_doc_number] => 20190065183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/170577 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13992095 [patent_doc_number] => 20190065205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => VARIABLE LENGTH INSTRUCTION PROCESSOR SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 16/153063 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14188941 [patent_doc_number] => 20190114176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/149050 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149050 [rel_patent_id] =>[rel_patent_doc_number] =>)