Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17824902 [patent_doc_number] => 11429850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Performing consecutive mac operations on a set of data using different kernels in a MAC circuit [patent_app_type] => utility [patent_app_number] => 16/040357 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/040357
Performing consecutive mac operations on a set of data using different kernels in a MAC circuit Jul 18, 2018 Issued
Array ( [id] => 16045977 [patent_doc_number] => 10684860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => High performance processor system and method based on general purpose units [patent_app_type] => utility [patent_app_number] => 16/029323 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 46 [patent_no_of_words] => 46136 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029323
High performance processor system and method based on general purpose units Jul 5, 2018 Issued
Array ( [id] => 15090333 [patent_doc_number] => 20190339977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Securing Conditional Speculative Instruction Execution [patent_app_type] => utility [patent_app_number] => 16/028750 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028750 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/028750
Securing conditional speculative instruction execution Jul 5, 2018 Issued
Array ( [id] => 15757701 [patent_doc_number] => 10620962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Appratus and method for using predicted result values [patent_app_type] => utility [patent_app_number] => 16/025116 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9886 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/025116
Appratus and method for using predicted result values Jul 1, 2018 Issued
Array ( [id] => 17031432 [patent_doc_number] => 11093243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Vector interleaving in a data processing apparatus [patent_app_type] => utility [patent_app_number] => 16/630622 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8462 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16630622 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/630622
Vector interleaving in a data processing apparatus Jul 1, 2018 Issued
Array ( [id] => 16185997 [patent_doc_number] => 10719329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Apparatus and method for using predicted result values [patent_app_type] => utility [patent_app_number] => 16/021178 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021178
Apparatus and method for using predicted result values Jun 27, 2018 Issued
Array ( [id] => 15638513 [patent_doc_number] => 10592250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-17 [patent_title] => Self-refill for instruction buffer [patent_app_type] => utility [patent_app_number] => 16/014646 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 12117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014646 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014646
Self-refill for instruction buffer Jun 20, 2018 Issued
Array ( [id] => 13845249 [patent_doc_number] => 20190026109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => INSTRUCTIONS AND LOGIC FOR VECTOR BIT FIELD COMPRESSION AND EXPANSION [patent_app_type] => utility [patent_app_number] => 16/010908 [patent_app_country] => US [patent_app_date] => 2018-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16010908 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/010908
Instructions and logic for vector bit field compression and expansion Jun 17, 2018 Issued
Array ( [id] => 15805585 [patent_doc_number] => 20200125935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => SEMICONDUCTOR DEVICE HAVING NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 16/621305 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16621305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/621305
Semiconductor device having neural network Jun 10, 2018 Issued
Array ( [id] => 13797497 [patent_doc_number] => 20190012287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP [patent_app_type] => utility [patent_app_number] => 15/995409 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15995409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/995409
Microcontroller programmable system on a chip May 31, 2018 Issued
Array ( [id] => 15472549 [patent_doc_number] => 10552149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Data processing device [patent_app_type] => utility [patent_app_number] => 15/987507 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987507
Data processing device May 22, 2018 Issued
Array ( [id] => 13417363 [patent_doc_number] => 20180260224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => EXECUTING SYSTEM CALL VECTORED INSTRUCTIONS IN A MULTI-SLICE PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/980874 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980874
Executing system call vectored instructions in a multi-slice processor May 15, 2018 Issued
Array ( [id] => 15886865 [patent_doc_number] => 10649777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Hardware-based data prefetching based on loop-unrolled instructions [patent_app_type] => utility [patent_app_number] => 15/978245 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4049 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978245 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/978245
Hardware-based data prefetching based on loop-unrolled instructions May 13, 2018 Issued
Array ( [id] => 17309482 [patent_doc_number] => 11210600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Multi-qubit entangling gate using a frequency-modulated tunable coupler [patent_app_type] => utility [patent_app_number] => 15/975011 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8401 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975011 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975011
Multi-qubit entangling gate using a frequency-modulated tunable coupler May 8, 2018 Issued
Array ( [id] => 16032243 [patent_doc_number] => 10678540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Arithmetic operation with shift [patent_app_type] => utility [patent_app_number] => 15/973663 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15973663 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/973663
Arithmetic operation with shift May 7, 2018 Issued
Array ( [id] => 13403575 [patent_doc_number] => 20180253330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => METHODS AND SYSTEMS FOR CONVERTING A RELATED GROUP OF PHYSICAL MACHINES TO VIRTUAL MACHINES [patent_app_type] => utility [patent_app_number] => 15/972211 [patent_app_country] => US [patent_app_date] => 2018-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972211 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972211
Methods and systems for converting a related group of physical machines to virtual machines May 5, 2018 Issued
Array ( [id] => 15854663 [patent_doc_number] => 10642615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => System and method for dynamic accuracy and threshold control for branch classification [patent_app_type] => utility [patent_app_number] => 15/964320 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964320
System and method for dynamic accuracy and threshold control for branch classification Apr 26, 2018 Issued
Array ( [id] => 16248331 [patent_doc_number] => 10747691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Memory device, a dual inline memory module, a storage device, an apparatus for storing, a method for storing, a computer program, a machine readable storage, and a machine readable medium [patent_app_type] => utility [patent_app_number] => 15/949095 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6123 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949095
Memory device, a dual inline memory module, a storage device, an apparatus for storing, a method for storing, a computer program, a machine readable storage, and a machine readable medium Apr 9, 2018 Issued
Array ( [id] => 13483061 [patent_doc_number] => 20180293073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => CACHE STORING DATA FETCHED BY ADDRESS CALCULATING LOAD INSTRUCTION WITH LABEL USED AS ASSOCIATED NAME FOR CONSUMING INSTRUCTION TO REFER [patent_app_type] => utility [patent_app_number] => 15/944655 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944655
Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer Apr 2, 2018 Issued
Array ( [id] => 14935061 [patent_doc_number] => 20190303168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => APPARATUS, METHODS, AND SYSTEMS FOR CONDITIONAL QUEUES IN A CONFIGURABLE SPATIAL ACCELERATOR [patent_app_type] => utility [patent_app_number] => 15/944761 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 91907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944761 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944761
Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator Apr 2, 2018 Issued
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