Eliseo Ramos Feliciano

Array ( [id] => 15670503 [patent_doc_number] => 10599481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Scheduler for amp architecture using a closed loop performance controller and deferred inter-processor interrupts [patent_app_type] => utility [patent_app_number] => 15/870770 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 30495 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14585351 [patent_doc_number] => 20190220284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => DYNAMIC DETECTION AND PREDICTION FOR STORE-DEPENDENT BRANCHES [patent_app_type] => utility [patent_app_number] => 15/870595 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13595255 [patent_doc_number] => 20180349176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SCHEDULER FOR AMP ARCHITECTURE WITH CLOSED LOOP PERFORMANCE CONTROLLER [patent_app_type] => utility [patent_app_number] => 15/870763 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16818790 [patent_doc_number] => 11003620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Systolic array of pipelined processing engines for implementing dynamic programming algorithms [patent_app_type] => utility [patent_app_number] => 15/853303 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16818790 [patent_doc_number] => 11003620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Systolic array of pipelined processing engines for implementing dynamic programming algorithms [patent_app_type] => utility [patent_app_number] => 15/853303 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15886873 [patent_doc_number] => 10649781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Enhanced performance-aware instruction scheduling [patent_app_type] => utility [patent_app_number] => 15/842955 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4604 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13579865 [patent_doc_number] => 20180341481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => GENERATING AND VERIFYING HARDWARE INSTRUCTION TRACES INCLUDING MEMORY DATA CONTENTS [patent_app_type] => utility [patent_app_number] => 15/817622 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12234868 [patent_doc_number] => 20180067731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'APPARATUS AND METHOD FOR EFFICIENT CALL/RETURN EMULATION USING A DUAL RETURN STACK BUFFER' [patent_app_type] => utility [patent_app_number] => 15/813021 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12241984 [patent_doc_number] => 20180074847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'DYNAMIC PREDICTION OF HARDWARE TRANSACTION RESOURCE REQUIREMENTS' [patent_app_type] => utility [patent_app_number] => 15/804321 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 19995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12221755 [patent_doc_number] => 20180060115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'DYNAMIC PREDICTION OF HARDWARE TRANSACTION RESOURCE REQUIREMENTS' [patent_app_type] => utility [patent_app_number] => 15/804194 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 19968 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14235091 [patent_doc_number] => 20190129718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => PACKED 16 BITS INSTRUCTION PIPELINE [patent_app_type] => utility [patent_app_number] => 15/799560 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14175561 [patent_doc_number] => 10261795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Instruction and logic for processing text strings [patent_app_type] => utility [patent_app_number] => 15/797524 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11569 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13830401 [patent_doc_number] => 20190018685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => LOW LATENCY EXECUTION OF FLOATING-POINT RECORD FORM INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 15/796135 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14952707 [patent_doc_number] => 10437618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => System and method of emulating execution of files [patent_app_type] => utility [patent_app_number] => 15/730958 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8132 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14161867 [patent_doc_number] => 20190108036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => STACK FRAME UNWINDING FOR EXCEPTION HANDLING [patent_app_type] => utility [patent_app_number] => 15/730713 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16787961 [patent_doc_number] => 10990394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Systems and methods for mixed instruction multiple data (xIMD) computing [patent_app_type] => utility [patent_app_number] => 15/719109 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13782539 [patent_doc_number] => 20190004808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => CENTRALIZED MEMORY MANAGEMENT FOR MULTIPLE DEVICE STREAMS [patent_app_type] => utility [patent_app_number] => 15/713096 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14076611 [patent_doc_number] => 20190087193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => TRAINING AND UTILIZATION OF NEURAL BRANCH PREDICTOR [patent_app_type] => utility [patent_app_number] => 15/712112 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14076609 [patent_doc_number] => 20190087192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => SLICE CONSTRUCTION FOR PRE-EXECUTING DATA DEPENDENT LOADS [patent_app_type] => utility [patent_app_number] => 15/712119 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14735525 [patent_doc_number] => 10387162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Effective address table with multiple taken branch handling for out-of-order processors [patent_app_type] => utility [patent_app_number] => 15/709777 [patent_app_country] => US [patent_app_date] => 2017-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12731 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15709777 [rel_patent_id] =>[rel_patent_doc_number] =>)