Eliseo Ramos Feliciano

Array ( [id] => 12532344 [patent_doc_number] => 10007636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Microcontroller programmable system on a chip [patent_app_type] => utility [patent_app_number] => 15/455393 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 36 [patent_no_of_words] => 17765 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14123489 [patent_doc_number] => 10248604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Microcontroller programmable system on a chip [patent_app_type] => utility [patent_app_number] => 15/453492 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 36 [patent_no_of_words] => 17755 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16551591 [patent_doc_number] => 10884750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Strideshift instruction for transposing bits inside vector register [patent_app_type] => utility [patent_app_number] => 16/474888 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 18489 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16474888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13948717 [patent_doc_number] => 10210134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => General-purpose parallel computing architecture [patent_app_type] => utility [patent_app_number] => 15/439777 [patent_app_country] => US [patent_app_date] => 2017-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 14525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11958139 [patent_doc_number] => 20170262290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'CAUSING AN INTERRUPT BASED ON EVENT COUNT' [patent_app_type] => utility [patent_app_number] => 15/438679 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14250093 [patent_doc_number] => 10275246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Programmable linear feedback shift register [patent_app_type] => utility [patent_app_number] => 15/433032 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4628 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13157581 [patent_doc_number] => 10095515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Compressed instruction format [patent_app_type] => utility [patent_app_number] => 15/431652 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11665293 [patent_doc_number] => 20170154012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'ASYMMETRIC PERFORMANCE MULTICORE ARCHITECTURE WITH SAME INSTRUCTION SET ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/431527 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4016 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11651452 [patent_doc_number] => 20170147353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/426276 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11629526 [patent_doc_number] => 20170139715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING DELTA DECODING ON PACKED DATA ELEMENTS' [patent_app_type] => utility [patent_app_number] => 15/419888 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12775381 [patent_doc_number] => 20180150295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => METHODS FOR EXECUTING A COMPUTER INSTRUCTION AND APPARATUSES USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/403524 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14555419 [patent_doc_number] => 10346171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures [patent_app_type] => utility [patent_app_number] => 15/402825 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 20037 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15402825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11951316 [patent_doc_number] => 20170255466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'EVENT-DRIVEN DESIGN SIMULATION' [patent_app_type] => utility [patent_app_number] => 15/400004 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 19952 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13269307 [patent_doc_number] => 10146738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Hardware accelerator architecture for processing very-sparse and hyper-sparse matrix data [patent_app_type] => utility [patent_app_number] => 15/396511 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 52 [patent_no_of_words] => 23924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14856545 [patent_doc_number] => 10416999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Processors, methods, and systems with a configurable spatial accelerator [patent_app_type] => utility [patent_app_number] => 15/396395 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 66 [patent_no_of_words] => 40373 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12892165 [patent_doc_number] => 20180189230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => PROCESSOR IN NON-VOLATILE STORAGE MEMORY [patent_app_type] => utility [patent_app_number] => 15/395415 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12891649 [patent_doc_number] => 20180189058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => Systems, Apparatuses, and Methods for Arithmetic Recurrence [patent_app_type] => utility [patent_app_number] => 15/396184 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14202727 [patent_doc_number] => 10268479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Systems, apparatuses, and methods for broadcast compare addition [patent_app_type] => utility [patent_app_number] => 15/396199 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 20212 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14034373 [patent_doc_number] => 10228937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Programmable matrix processing engine [patent_app_type] => utility [patent_app_number] => 15/395654 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14778 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14034375 [patent_doc_number] => 10228938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Apparatus and method for instruction-based flop accounting [patent_app_type] => utility [patent_app_number] => 15/396345 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 15164 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396345 [rel_patent_id] =>[rel_patent_doc_number] =>)