
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12513597
[patent_doc_number] => 10001997
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-19
[patent_title] => Prioritizing instructions based on type
[patent_app_type] => utility
[patent_app_number] => 15/387394
[patent_app_country] => US
[patent_app_date] => 2016-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 11089
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387394
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/387394 | Prioritizing instructions based on type | Dec 20, 2016 | Issued |
Array
(
[id] => 11516268
[patent_doc_number] => 20170083342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'PATTERN BASED BRANCH PREDICTION'
[patent_app_type] => utility
[patent_app_number] => 15/373510
[patent_app_country] => US
[patent_app_date] => 2016-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4168
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15373510
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/373510 | Pattern based branch prediction | Dec 8, 2016 | Issued |
Array
(
[id] => 11629525
[patent_doc_number] => 20170139714
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-18
[patent_title] => 'CACHE STORING DATA FETCHED BY ADDRESS CALCULATING LOAD INSTRUCTION WITH LABEL USED AS ASSOCIATED NAME FOR CONSUMING INSTRUCTION TO REFER'
[patent_app_type] => utility
[patent_app_number] => 15/357943
[patent_app_country] => US
[patent_app_date] => 2016-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 15068
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357943
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/357943 | Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer | Nov 20, 2016 | Issued |
Array
(
[id] => 13948437
[patent_doc_number] => 10209993
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-19
[patent_title] => Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and branch pattern to generate conditional branch predictor indexes
[patent_app_type] => utility
[patent_app_number] => 15/333861
[patent_app_country] => US
[patent_app_date] => 2016-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7027
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333861
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/333861 | Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and branch pattern to generate conditional branch predictor indexes | Oct 24, 2016 | Issued |
Array
(
[id] => 12611769
[patent_doc_number] => 20180095753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => PIPELINED PROCESSOR WITH MULTI-ISSUE MICROCODE UNIT HAVING LOCAL BRANCH DECODER
[patent_app_type] => utility
[patent_app_number] => 15/332403
[patent_app_country] => US
[patent_app_date] => 2016-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6218
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15332403
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/332403 | Pipelined processor with multi-issue microcode unit having local branch decoder | Oct 23, 2016 | Issued |
Array
(
[id] => 12393102
[patent_doc_number] => 09965282
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-08
[patent_title] => Systems, apparatuses, and methods for performing delta encoding on packed data elements
[patent_app_type] => utility
[patent_app_number] => 15/290958
[patent_app_country] => US
[patent_app_date] => 2016-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 25
[patent_no_of_words] => 15755
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290958
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/290958 | Systems, apparatuses, and methods for performing delta encoding on packed data elements | Oct 10, 2016 | Issued |
Array
(
[id] => 11403666
[patent_doc_number] => 20170024204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-26
[patent_title] => 'VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION'
[patent_app_type] => utility
[patent_app_number] => 15/286794
[patent_app_country] => US
[patent_app_date] => 2016-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 18610
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15286794
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/286794 | Vector Galois field multiply sum and accumulate instruction | Oct 5, 2016 | Issued |
Array
(
[id] => 13403535
[patent_doc_number] => 20180253310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-06
[patent_title] => VECTOR LOAD INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 15/759914
[patent_app_country] => US
[patent_app_date] => 2016-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14966
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15759914
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/759914 | Vector load instruction | Sep 4, 2016 | Issued |
Array
(
[id] => 12207462
[patent_doc_number] => 20180052688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-22
[patent_title] => 'MEMORY MOVE INSTRUCTION SEQUENCE TARGETING AN ACCELERATOR SWITCHBOARD'
[patent_app_type] => utility
[patent_app_number] => 15/243650
[patent_app_country] => US
[patent_app_date] => 2016-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 27439
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15243650
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/243650 | Memory move instruction sequence targeting an accelerator switchboard | Aug 21, 2016 | Issued |
Array
(
[id] => 16894950
[patent_doc_number] => 11036503
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-15
[patent_title] => Predicate indicator generation for vector processing operations
[patent_app_type] => utility
[patent_app_number] => 15/236769
[patent_app_country] => US
[patent_app_date] => 2016-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 6464
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236769
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/236769 | Predicate indicator generation for vector processing operations | Aug 14, 2016 | Issued |
Array
(
[id] => 16879804
[patent_doc_number] => 11029951
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-08
[patent_title] => Smallest or largest value element determination
[patent_app_type] => utility
[patent_app_number] => 15/237085
[patent_app_country] => US
[patent_app_date] => 2016-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 18345
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15237085
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/237085 | Smallest or largest value element determination | Aug 14, 2016 | Issued |
Array
(
[id] => 11272539
[patent_doc_number] => 20160335086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-17
[patent_title] => 'Read and Write Masks Update Instruction for Vectorization of Recursive Computations Over Independent Data'
[patent_app_type] => utility
[patent_app_number] => 15/219185
[patent_app_country] => US
[patent_app_date] => 2016-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11299
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219185
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/219185 | Read and write masks update instruction for vectorization of recursive computations over independent data | Jul 24, 2016 | Issued |
Array
(
[id] => 11131260
[patent_doc_number] => 20160328235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-10
[patent_title] => 'INSTRUCTION FOR IMPLEMENTING ITERATIONS HAVING AN ITERATION DEPENDENT CONDITION WITH A VECTOR LOOP'
[patent_app_type] => utility
[patent_app_number] => 15/214348
[patent_app_country] => US
[patent_app_date] => 2016-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 17473
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15214348
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/214348 | Instruction for implementing iterations having an iteration dependent condition with a vector loop | Jul 18, 2016 | Issued |
Array
(
[id] => 12120939
[patent_doc_number] => 20180004524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'REGISTER RECLAMATION'
[patent_app_type] => utility
[patent_app_number] => 15/201403
[patent_app_country] => US
[patent_app_date] => 2016-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 29647
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201403
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/201403 | Register reclamation | Jul 1, 2016 | Issued |
Array
(
[id] => 12121043
[patent_doc_number] => 20180004628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'COOPERATIVE TRIGGERING'
[patent_app_type] => utility
[patent_app_number] => 15/201405
[patent_app_country] => US
[patent_app_date] => 2016-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 27567
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201405
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/201405 | Cooperative triggering | Jul 1, 2016 | Issued |
Array
(
[id] => 12120932
[patent_doc_number] => 20180004518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'Systems, Apparatuses, and Methods for Strided Load'
[patent_app_type] => utility
[patent_app_number] => 15/201391
[patent_app_country] => US
[patent_app_date] => 2016-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 18273
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201391
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/201391 | Systems, apparatuses, and methods for strided load | Jul 1, 2016 | Issued |
Array
(
[id] => 12120924
[patent_doc_number] => 20180004510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'INTERRUPTIBLE AND RESTARTABLE MATRIX MULTIPLICATION INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 15/201442
[patent_app_country] => US
[patent_app_date] => 2016-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 19797
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201442
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/201442 | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems | Jul 1, 2016 | Issued |
Array
(
[id] => 12120928
[patent_doc_number] => 20180004514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'Systems, Apparatuses, and Methods for Cumulative Summation'
[patent_app_type] => utility
[patent_app_number] => 15/201390
[patent_app_country] => US
[patent_app_date] => 2016-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 17539
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201390
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/201390 | Systems, apparatuses, and methods for cumulative summation | Jul 1, 2016 | Issued |
Array
(
[id] => 13143553
[patent_doc_number] => 10089110
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-02
[patent_title] => Systems, apparatuses, and methods for cumulative product
[patent_app_type] => utility
[patent_app_number] => 15/201392
[patent_app_country] => US
[patent_app_date] => 2016-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 16518
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201392
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/201392 | Systems, apparatuses, and methods for cumulative product | Jul 1, 2016 | Issued |
Array
(
[id] => 12120938
[patent_doc_number] => 20180004525
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR SNOOPING PERSISTENT MEMORY STORE ADDRESSES'
[patent_app_type] => utility
[patent_app_number] => 15/201446
[patent_app_country] => US
[patent_app_date] => 2016-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 16888
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201446
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/201446 | Systems, apparatuses, and methods for snooping persistent memory store addresses | Jul 1, 2016 | Issued |