Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19267728 [patent_doc_number] => 20240211431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => TECHNOLOGY FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK [patent_app_type] => utility [patent_app_number] => 18/601598 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601598
Technology for controlling peak power by dividing clock Mar 10, 2024 Issued
Array ( [id] => 20344804 [patent_doc_number] => 12468535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Cooperative instruction prefetch on multicore system [patent_app_type] => utility [patent_app_number] => 18/595866 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1237 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595866
Cooperative instruction prefetch on multicore system Mar 4, 2024 Issued
Array ( [id] => 19499362 [patent_doc_number] => 20240338380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => DATA TRANSFORM OPERATIONS IN A DATA TRANSFORM ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/596556 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596556 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596556
DATA TRANSFORM OPERATIONS IN A DATA TRANSFORM ACCELERATOR Mar 4, 2024 Pending
Array ( [id] => 19251133 [patent_doc_number] => 20240202123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => STREAMING ENGINE WITH VARIABLE STREAM TEMPLATE FORMAT [patent_app_type] => utility [patent_app_number] => 18/594091 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594091
Streaming engine with variable stream template format Mar 3, 2024 Issued
Array ( [id] => 19251133 [patent_doc_number] => 20240202123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => STREAMING ENGINE WITH VARIABLE STREAM TEMPLATE FORMAT [patent_app_type] => utility [patent_app_number] => 18/594091 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594091
Streaming engine with variable stream template format Mar 3, 2024 Issued
Array ( [id] => 20137960 [patent_doc_number] => 20250245004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => SIGNIFICAND SHIFTING IN FLOATING POINT PROCESSING OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/428137 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428137 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428137
Significand shifting in floating point processing operations Jan 30, 2024 Issued
Array ( [id] => 20138145 [patent_doc_number] => 20250245189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => REARRANGING DATA AMONG PROCESSING ELEMENTS OF COMPUTATIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 18/424143 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424143
REARRANGING DATA AMONG PROCESSING ELEMENTS OF COMPUTATIONAL MEMORY Jan 25, 2024 Pending
Array ( [id] => 20138145 [patent_doc_number] => 20250245189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => REARRANGING DATA AMONG PROCESSING ELEMENTS OF COMPUTATIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 18/424143 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424143
REARRANGING DATA AMONG PROCESSING ELEMENTS OF COMPUTATIONAL MEMORY Jan 25, 2024 Pending
Array ( [id] => 19617366 [patent_doc_number] => 20240403046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Load/Store Unit for a Tensor Engine and Methods for Loading or Storing a Tensor [patent_app_type] => utility [patent_app_number] => 18/423210 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423210
Load/store unit for a tensor engine and methods for loading or storing a tensor Jan 24, 2024 Issued
Array ( [id] => 20123200 [patent_doc_number] => 20250238231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => METHOD AND SYSTEM FOR EFFICIENT DATA MOVEMENT IN VECTOR PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/415926 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415926
Method and system for efficient data movement in vector processors Jan 17, 2024 Issued
Array ( [id] => 19267560 [patent_doc_number] => 20240211263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => NEURAL PROCESSOR AND METHOD FOR FETCHING INSTRUCTIONS THEREOF [patent_app_type] => utility [patent_app_number] => 18/415523 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415523
NEURAL PROCESSOR AND METHOD FOR FETCHING INSTRUCTIONS THEREOF Jan 16, 2024 Pending
Array ( [id] => 19189806 [patent_doc_number] => 20240168719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => DUAL VECTOR ARITHMETIC LOGIC UNIT [patent_app_type] => utility [patent_app_number] => 18/414164 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414164
Dual vector arithmetic logic unit Jan 15, 2024 Issued
Array ( [id] => 20265780 [patent_doc_number] => 12436771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Performing fused shift and logical operations in processor-based devices [patent_app_type] => utility [patent_app_number] => 18/400294 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3136 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400294
Performing fused shift and logical operations in processor-based devices Dec 28, 2023 Issued
Array ( [id] => 19084732 [patent_doc_number] => 20240111533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR TILE CONFIGURATION [patent_app_type] => utility [patent_app_number] => 18/534012 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534012 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534012
Systems, methods, and apparatus for tile configuration Dec 7, 2023 Issued
Array ( [id] => 19283783 [patent_doc_number] => 20240220259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DATA COMPRESSION USING INSTRUCTION SET ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/525083 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525083
DATA COMPRESSION USING INSTRUCTION SET ARCHITECTURE Nov 29, 2023 Pending
Array ( [id] => 19228301 [patent_doc_number] => 12007937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-11 [patent_title] => Multi-mode architecture for unifying matrix multiplication, 1x1 convolution and 3x3 convolution [patent_app_type] => utility [patent_app_number] => 18/523632 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 17809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523632
Multi-mode architecture for unifying matrix multiplication, 1x1 convolution and 3x3 convolution Nov 28, 2023 Issued
Array ( [id] => 20403604 [patent_doc_number] => 12493577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Digital signal processor (DSP) and electronic device using the same [patent_app_type] => utility [patent_app_number] => 18/512788 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512788 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512788
Digital signal processor (DSP) and electronic device using the same Nov 16, 2023 Issued
Array ( [id] => 20403604 [patent_doc_number] => 12493577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Digital signal processor (DSP) and electronic device using the same [patent_app_type] => utility [patent_app_number] => 18/512788 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512788 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512788
Digital signal processor (DSP) and electronic device using the same Nov 16, 2023 Issued
Array ( [id] => 19021941 [patent_doc_number] => 20240078112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => TECHNIQUES FOR DECOUPLED ACCESS-EXECUTE NEAR-MEMORY PROCESSING [patent_app_type] => utility [patent_app_number] => 18/388797 [patent_app_country] => US [patent_app_date] => 2023-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388797 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388797
Techniques for decoupled access-execute near-memory processing Nov 9, 2023 Issued
Array ( [id] => 20317186 [patent_doc_number] => 12455737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Neural network compute tile [patent_app_type] => utility [patent_app_number] => 18/505743 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4787 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505743
Neural network compute tile Nov 8, 2023 Issued
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