Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14149383 [patent_doc_number] => 10255072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Architectural register replacement for instructions that use multiple architectural registers [patent_app_type] => utility [patent_app_number] => 15/201310 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 15543 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201310
Architectural register replacement for instructions that use multiple architectural registers Jun 30, 2016 Issued
Array ( [id] => 12120927 [patent_doc_number] => 20180004513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'APPARATUSES, METHODS, AND SYSTEMS FOR ELEMENT SORTING OF VECTORS' [patent_app_type] => utility [patent_app_number] => 15/201138 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 22284 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201138 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201138
Apparatuses, methods, and systems for element sorting of vectors Jun 30, 2016 Issued
Array ( [id] => 12120936 [patent_doc_number] => 20180004522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'APPARATUSES, METHODS, AND SYSTEMS FOR MEMORY DISAMBIGUATION' [patent_app_type] => utility [patent_app_number] => 15/201218 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14699 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201218 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201218
Apparatuses, methods, and systems for memory disambiguation Jun 30, 2016 Issued
Array ( [id] => 15136979 [patent_doc_number] => 10481957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Processor and task processing method therefor, and storage medium [patent_app_type] => utility [patent_app_number] => 15/763996 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15763996 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/763996
Processor and task processing method therefor, and storage medium Jun 30, 2016 Issued
Array ( [id] => 13767281 [patent_doc_number] => 10175982 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => Storing taken branch information [patent_app_type] => utility [patent_app_number] => 15/184308 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/184308
Storing taken branch information Jun 15, 2016 Issued
Array ( [id] => 14952659 [patent_doc_number] => 10437594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Apparatus and method for transferring a plurality of data structures between memory and one or more vectors of data elements stored in a register bank [patent_app_type] => utility [patent_app_number] => 15/746559 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14924 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15746559 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/746559
Apparatus and method for transferring a plurality of data structures between memory and one or more vectors of data elements stored in a register bank Jun 14, 2016 Issued
Array ( [id] => 12474858 [patent_doc_number] => 09990204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Data processing [patent_app_type] => utility [patent_app_number] => 15/182335 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 5926 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/182335
Data processing Jun 13, 2016 Issued
Array ( [id] => 13891441 [patent_doc_number] => 10198268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Data processing [patent_app_type] => utility [patent_app_number] => 15/182385 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 6787 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182385 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/182385
Data processing Jun 13, 2016 Issued
Array ( [id] => 13212641 [patent_doc_number] => 10120690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-06 [patent_title] => Reservation station early age indicator generation [patent_app_type] => utility [patent_app_number] => 15/181183 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15181183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/181183
Reservation station early age indicator generation Jun 12, 2016 Issued
Array ( [id] => 14061753 [patent_doc_number] => 10235169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence [patent_app_type] => utility [patent_app_number] => 15/179504 [patent_app_country] => US [patent_app_date] => 2016-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7254 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15179504 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/179504
Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence Jun 9, 2016 Issued
Array ( [id] => 11086273 [patent_doc_number] => 20160283239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'GUEST INSTRUCTION BLOCK WITH NEAR BRANCHING AND FAR BRANCHING SEQUENCE CONSTRUCTION TO NATIVE INSTRUCTION BLOCK' [patent_app_type] => utility [patent_app_number] => 15/176079 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11462 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176079 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/176079
Guest instruction block with near branching and far branching sequence construction to native instruction block Jun 6, 2016 Issued
Array ( [id] => 14123135 [patent_doc_number] => 10248426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Direct register restore mechanism for distributed history buffers [patent_app_type] => utility [patent_app_number] => 15/163314 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6359 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163314 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163314
Direct register restore mechanism for distributed history buffers May 23, 2016 Issued
Array ( [id] => 12986056 [patent_doc_number] => 20170344379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => GENERATING A MASK VECTOR FOR DETERMINING A PROCESSOR INSTRUCTION ADDRESS USING AN INSTRUCTION TAG IN A MULTI-SLICE PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/162998 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162998 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/162998
Generating a mask vector for determining a processor instruction address using an instruction tag in a multi-slice processor May 23, 2016 Issued
Array ( [id] => 13055145 [patent_doc_number] => 10048963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Executing system call vectored instructions in a multi-slice processor [patent_app_type] => utility [patent_app_number] => 15/161461 [patent_app_country] => US [patent_app_date] => 2016-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7416 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161461 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/161461
Executing system call vectored instructions in a multi-slice processor May 22, 2016 Issued
Array ( [id] => 13664945 [patent_doc_number] => 10162634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Extendable conditional permute SIMD instructions [patent_app_type] => utility [patent_app_number] => 15/160217 [patent_app_country] => US [patent_app_date] => 2016-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15160217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/160217
Extendable conditional permute SIMD instructions May 19, 2016 Issued
Array ( [id] => 12352089 [patent_doc_number] => 09952872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Arithmetic processing device and processing method of arithmetic processing device [patent_app_type] => utility [patent_app_number] => 15/160308 [patent_app_country] => US [patent_app_date] => 2016-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15116 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15160308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/160308
Arithmetic processing device and processing method of arithmetic processing device May 19, 2016 Issued
Array ( [id] => 13186119 [patent_doc_number] => 10108580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => General-purpose parallel computing architecture [patent_app_type] => utility [patent_app_number] => 15/157218 [patent_app_country] => US [patent_app_date] => 2016-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12922 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157218 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/157218
General-purpose parallel computing architecture May 16, 2016 Issued
Array ( [id] => 11423541 [patent_doc_number] => 20170031686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'AGE BASED FAST INSTRUCTION ISSUE' [patent_app_type] => utility [patent_app_number] => 15/145835 [patent_app_country] => US [patent_app_date] => 2016-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145835 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/145835
Age based fast instruction issue May 3, 2016 Issued
Array ( [id] => 11042347 [patent_doc_number] => 20160239303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'MICROPROCESSOR USING COMPRESSED AND UNCOMPRESSED MICROCODE STORAGE' [patent_app_type] => utility [patent_app_number] => 15/140010 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15140010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/140010
Microprocessor using compressed and uncompressed microcode storage Apr 26, 2016 Issued
Array ( [id] => 11027412 [patent_doc_number] => 20160224368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'METHODS AND SYSTEMS FOR CONVERTING A RELATED GROUP OF PHYSICAL MACHINES TO VIRTUAL MACHINES' [patent_app_type] => utility [patent_app_number] => 15/095676 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095676 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095676
Methods and systems for converting a related group of physical machines to virtual machines Apr 10, 2016 Issued
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