Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11020018 [patent_doc_number] => 20160216971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING' [patent_app_type] => utility [patent_app_number] => 15/088043 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15088043 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/088043
Method and system to provide user-level multithreading Mar 30, 2016 Issued
Array ( [id] => 11365986 [patent_doc_number] => 20170003968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'PATTERN BASED BRANCH PREDICTION' [patent_app_type] => utility [patent_app_number] => 15/084884 [patent_app_country] => US [patent_app_date] => 2016-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4174 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15084884 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/084884
Pattern based branch prediction Mar 29, 2016 Issued
Array ( [id] => 15886869 [patent_doc_number] => 10649779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Variable latency pipe for interleaving instruction tags in a microprocessor [patent_app_type] => utility [patent_app_number] => 15/072670 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5152 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072670 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/072670
Variable latency pipe for interleaving instruction tags in a microprocessor Mar 16, 2016 Issued
Array ( [id] => 11944995 [patent_doc_number] => 20170249146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'BANDWIDTH REDUCTION FOR INSTRUCTION TRACING' [patent_app_type] => utility [patent_app_number] => 15/057111 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5330 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057111 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057111
BANDWIDTH REDUCTION FOR INSTRUCTION TRACING Feb 28, 2016 Abandoned
Array ( [id] => 11944993 [patent_doc_number] => 20170249144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'COMBINING LOADS OR STORES IN COMPUTER PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/055160 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15055160 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/055160
COMBINING LOADS OR STORES IN COMPUTER PROCESSING Feb 25, 2016 Abandoned
Array ( [id] => 13083027 [patent_doc_number] => 10061580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence [patent_app_type] => utility [patent_app_number] => 15/053419 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7210 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053419 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/053419
Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence Feb 24, 2016 Issued
Array ( [id] => 12331656 [patent_doc_number] => 09946546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Processor and instruction code generation device [patent_app_type] => utility [patent_app_number] => 15/053798 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12737 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053798 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/053798
Processor and instruction code generation device Feb 24, 2016 Issued
Array ( [id] => 12531999 [patent_doc_number] => 10007520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-26 [patent_title] => Systems and methods for using alternate computer instruction sets [patent_app_type] => utility [patent_app_number] => 15/053194 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/053194
Systems and methods for using alternate computer instruction sets Feb 24, 2016 Issued
Array ( [id] => 12571038 [patent_doc_number] => 10019264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => System and method for contextual vectorization of instructions at runtime [patent_app_type] => utility [patent_app_number] => 15/052765 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052765 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052765
System and method for contextual vectorization of instructions at runtime Feb 23, 2016 Issued
Array ( [id] => 11938547 [patent_doc_number] => 20170242697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'System and Method for Executing an Instruction to Permute a Mask' [patent_app_type] => utility [patent_app_number] => 15/052801 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052801 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052801
System and method for executing an instruction to permute a mask Feb 23, 2016 Issued
Array ( [id] => 12532002 [patent_doc_number] => 10007521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-26 [patent_title] => Banked physical register data flow architecture in out-of-order processors [patent_app_type] => utility [patent_app_number] => 15/051465 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 18688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051465 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051465
Banked physical register data flow architecture in out-of-order processors Feb 22, 2016 Issued
Array ( [id] => 12513579 [patent_doc_number] => 10001991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Data processing device [patent_app_type] => utility [patent_app_number] => 15/015565 [patent_app_country] => US [patent_app_date] => 2016-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7962 [patent_no_of_claims] => 124 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15015565 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/015565
Data processing device Feb 3, 2016 Issued
Array ( [id] => 12228914 [patent_doc_number] => 09916159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Programmable linear feedback shift register' [patent_app_type] => utility [patent_app_number] => 14/995588 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4703 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995588 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995588
Programmable linear feedback shift register Jan 13, 2016 Issued
Array ( [id] => 11716907 [patent_doc_number] => 20170185406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'METHODS AND SYSTEMS FOR MANAGING AN INSTRUCTION SEQUENCE WITH A DIVERGENT CONTROL FLOW IN A SIMT ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/982257 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10998 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982257 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/982257
Methods and systems for managing an instruction sequence with a divergent control flow in a SIMT architecture Dec 28, 2015 Issued
Array ( [id] => 12474855 [patent_doc_number] => 09990203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Hardware accuracy counters for application precision and quality feedback [patent_app_type] => utility [patent_app_number] => 14/981310 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14981310 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/981310
Hardware accuracy counters for application precision and quality feedback Dec 27, 2015 Issued
Array ( [id] => 13003849 [patent_doc_number] => 10025593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Generating and executing a control flow [patent_app_type] => utility [patent_app_number] => 14/980024 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980024
Generating and executing a control flow Dec 27, 2015 Issued
Array ( [id] => 13003849 [patent_doc_number] => 10025593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Generating and executing a control flow [patent_app_type] => utility [patent_app_number] => 14/980024 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980024
Generating and executing a control flow Dec 27, 2015 Issued
Array ( [id] => 13003849 [patent_doc_number] => 10025593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Generating and executing a control flow [patent_app_type] => utility [patent_app_number] => 14/980024 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980024
Generating and executing a control flow Dec 27, 2015 Issued
Array ( [id] => 13003849 [patent_doc_number] => 10025593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Generating and executing a control flow [patent_app_type] => utility [patent_app_number] => 14/980024 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980024
Generating and executing a control flow Dec 27, 2015 Issued
Array ( [id] => 12495213 [patent_doc_number] => 09996356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/998299 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7804 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998299 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998299
Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor Dec 25, 2015 Issued
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