
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11716908
[patent_doc_number] => 20170185407
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-29
[patent_title] => 'Method and apparatus for loop-invariant instruction detection and elimination'
[patent_app_type] => utility
[patent_app_number] => 14/998295
[patent_app_country] => US
[patent_app_date] => 2015-12-26
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998295
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/998295 | Method and apparatus for loop-invariant instruction detection and elimination | Dec 25, 2015 | Issued |
Array
(
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[patent_issue_date] => 2017-03-23
[patent_title] => 'Dynamic generation of null instructions'
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[patent_app_number] => 14/998147
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/998147 | Dynamic generation of null instructions | Dec 22, 2015 | Issued |
Array
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[patent_doc_number] => 20170177342
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[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'Instructions and Logic for Vector Bit Field Compression and Expansion'
[patent_app_type] => utility
[patent_app_number] => 14/979322
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[patent_app_date] => 2015-12-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/979322 | Instructions and logic for vector bit field compression and expansion | Dec 21, 2015 | Issued |
Array
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[patent_doc_number] => 20170177366
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[patent_issue_date] => 2017-06-22
[patent_title] => 'SELECTIVE STORING OF PREVIOUSLY DECODED INSTRUCTIONS OF FREQUENTLY-CALLED INSTRUCTION SEQUENCES IN AN INSTRUCTION SEQUENCE BUFFER TO BE EXECUTED BY A PROCESSOR'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/977840 | Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor | Dec 21, 2015 | Issued |
Array
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[patent_doc_number] => 20170177340
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[patent_title] => 'VECTOR STORE/LOAD INSTRUCTIONS FOR ARRAY OF STRUCTURES'
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Array
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[patent_title] => 'Age based fast instruction issue'
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Array
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[patent_title] => 'APPARATUS AND METHOD FOR RETRIEVING ELEMENTS FROM A LINKED STRUCTURE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/979236 | Apparatus and method for retrieving elements from a linked structure | Dec 21, 2015 | Issued |
Array
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[patent_doc_number] => 20170177363
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[patent_title] => 'Instructions and Logic for Load-Indices-and-Gather Operations'
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[patent_app_number] => 14/979231
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/979231 | Instructions and Logic for Load-Indices-and-Gather Operations | Dec 21, 2015 | Abandoned |
Array
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[id] => 14457535
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[patent_issue_date] => 2019-06-18
[patent_title] => Lightweight interrupts for condition checking
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[patent_title] => 'PERFORMANCE OPTIMIZATION ENGINE FOR PROCESSOR PARAMETER ADJUSTMENT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/958153 | Performance optimization engine for processor parameter adjustment | Dec 2, 2015 | Issued |
Array
(
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[patent_title] => 'Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold'
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/852116 | Methods for single-owner multi-consumer work queues for repeatable tasks | Sep 10, 2015 | Issued |
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/839008 | Deferral instruction for managing transactional aborts in transactional memory computing environments | Aug 27, 2015 | Issued |
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