Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11716908 [patent_doc_number] => 20170185407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'Method and apparatus for loop-invariant instruction detection and elimination' [patent_app_type] => utility [patent_app_number] => 14/998295 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8028 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998295 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998295
Method and apparatus for loop-invariant instruction detection and elimination Dec 25, 2015 Issued
Array ( [id] => 11516251 [patent_doc_number] => 20170083325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Dynamic generation of null instructions' [patent_app_type] => utility [patent_app_number] => 14/998147 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998147
Dynamic generation of null instructions Dec 22, 2015 Issued
Array ( [id] => 11708844 [patent_doc_number] => 20170177342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instructions and Logic for Vector Bit Field Compression and Expansion' [patent_app_type] => utility [patent_app_number] => 14/979322 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22491 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979322 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979322
Instructions and logic for vector bit field compression and expansion Dec 21, 2015 Issued
Array ( [id] => 11708866 [patent_doc_number] => 20170177366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'SELECTIVE STORING OF PREVIOUSLY DECODED INSTRUCTIONS OF FREQUENTLY-CALLED INSTRUCTION SEQUENCES IN AN INSTRUCTION SEQUENCE BUFFER TO BE EXECUTED BY A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/977840 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11821 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977840 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977840
Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor Dec 21, 2015 Issued
Array ( [id] => 11708841 [patent_doc_number] => 20170177340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'VECTOR STORE/LOAD INSTRUCTIONS FOR ARRAY OF STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/977782 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13835 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977782
Vector store/load instructions for array of structures Dec 21, 2015 Issued
Array ( [id] => 11780688 [patent_doc_number] => 09389870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-12 [patent_title] => 'Age based fast instruction issue' [patent_app_type] => utility [patent_app_number] => 14/977962 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6705 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977962 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977962
Age based fast instruction issue Dec 21, 2015 Issued
Array ( [id] => 11708842 [patent_doc_number] => 20170177341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'APPARATUS AND METHOD FOR RETRIEVING ELEMENTS FROM A LINKED STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/979236 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14864 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979236 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979236
Apparatus and method for retrieving elements from a linked structure Dec 21, 2015 Issued
Array ( [id] => 11708864 [patent_doc_number] => 20170177363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instructions and Logic for Load-Indices-and-Gather Operations' [patent_app_type] => utility [patent_app_number] => 14/979231 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 30610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979231 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979231
Instructions and Logic for Load-Indices-and-Gather Operations Dec 21, 2015 Abandoned
Array ( [id] => 14457535 [patent_doc_number] => 10324728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Lightweight interrupts for condition checking [patent_app_type] => utility [patent_app_number] => 14/972219 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972219 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972219
Lightweight interrupts for condition checking Dec 16, 2015 Issued
Array ( [id] => 11672371 [patent_doc_number] => 20170161093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'PERFORMANCE OPTIMIZATION ENGINE FOR PROCESSOR PARAMETER ADJUSTMENT' [patent_app_type] => utility [patent_app_number] => 14/958153 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958153 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/958153
Performance optimization engine for processor parameter adjustment Dec 2, 2015 Issued
Array ( [id] => 11889593 [patent_doc_number] => 09760153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold' [patent_app_type] => utility [patent_app_number] => 14/934772 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14934772 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/934772
Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold Nov 5, 2015 Issued
Array ( [id] => 10710925 [patent_doc_number] => 20160057072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'OPTIMIZING RESOURCE CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 14/932260 [patent_app_country] => US [patent_app_date] => 2015-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14932260 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/932260
Optimizing resource configurations Nov 3, 2015 Issued
Array ( [id] => 14331185 [patent_doc_number] => 10296612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Sorting system [patent_app_type] => utility [patent_app_number] => 14/869374 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869374 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869374
Sorting system Sep 28, 2015 Issued
Array ( [id] => 11896718 [patent_doc_number] => 09766650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Microcontroller programmable system on a chip with programmable interconnect' [patent_app_type] => utility [patent_app_number] => 14/866439 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 36 [patent_no_of_words] => 18367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866439 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/866439
Microcontroller programmable system on a chip with programmable interconnect Sep 24, 2015 Issued
Array ( [id] => 10658411 [patent_doc_number] => 20160004556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'DYNAMIC PREDICTION OF HARDWARE TRANSACTION RESOURCE REQUIREMENTS' [patent_app_type] => utility [patent_app_number] => 14/854149 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 19971 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854149 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/854149
Dynamic prediction of hardware transaction resource requirements Sep 14, 2015 Issued
Array ( [id] => 10658428 [patent_doc_number] => 20160004572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'METHODS FOR SINGLE-OWNER MULTI-CONSUMER WORK QUEUES FOR REPEATABLE TASKS' [patent_app_type] => utility [patent_app_number] => 14/852116 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/852116
Methods for single-owner multi-consumer work queues for repeatable tasks Sep 10, 2015 Issued
Array ( [id] => 10493770 [patent_doc_number] => 20150378792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'DEFERRAL INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 14/839008 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21191 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14839008 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/839008
Deferral instruction for managing transactional aborts in transactional memory computing environments Aug 27, 2015 Issued
Array ( [id] => 10478207 [patent_doc_number] => 20150363223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'PREDICTING THE LENGTH OF A TRANSACTION' [patent_app_type] => utility [patent_app_number] => 14/837164 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 17292 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837164 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837164
Predicting the length of a transaction Aug 26, 2015 Issued
Array ( [id] => 12932935 [patent_doc_number] => 09830185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Indicating nearing the completion of a transaction [patent_app_type] => utility [patent_app_number] => 14/831966 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 17308 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831966 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/831966
Indicating nearing the completion of a transaction Aug 20, 2015 Issued
Array ( [id] => 12194569 [patent_doc_number] => 09898297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Issuing instructions to multiple execution units' [patent_app_type] => utility [patent_app_number] => 14/830704 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 51 [patent_no_of_words] => 49711 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830704 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830704
Issuing instructions to multiple execution units Aug 18, 2015 Issued
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