Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10651070 [patent_doc_number] => 09367322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-14 [patent_title] => 'Age based fast instruction issue' [patent_app_type] => utility [patent_app_number] => 14/809291 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809291 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/809291
Age based fast instruction issue Jul 26, 2015 Issued
Array ( [id] => 10416846 [patent_doc_number] => 20150301856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'TASK PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/792342 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 23217 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792342 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792342
Task processor Jul 5, 2015 Issued
Array ( [id] => 11830601 [patent_doc_number] => 09727343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Apparatus and method for handling exception events' [patent_app_type] => utility [patent_app_number] => 14/788848 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10304 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788848 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/788848
Apparatus and method for handling exception events Jun 30, 2015 Issued
Array ( [id] => 12291099 [patent_doc_number] => 09934041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Pattern based branch prediction [patent_app_type] => utility [patent_app_number] => 14/789065 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14789065 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/789065
Pattern based branch prediction Jun 30, 2015 Issued
Array ( [id] => 13679489 [patent_doc_number] => 20160378481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INSTRUCTION AND LOGIC FOR ENCODED WORD INSTRUCTION COMPRESSION [patent_app_type] => utility [patent_app_number] => 14/750638 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750638 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750638
Instruction and logic for encoded word instruction compression Jun 24, 2015 Issued
Array ( [id] => 10493712 [patent_doc_number] => 20150378734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/749955 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14749955 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/749955
System and methods for expandably wide processor instructions Jun 24, 2015 Issued
Array ( [id] => 13679499 [patent_doc_number] => 20160378486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => METHOD AND APPARATUS FOR EXECUTION MODE SELECTION [patent_app_type] => utility [patent_app_number] => 14/750212 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750212 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750212
Method and apparatus for execution mode selection Jun 24, 2015 Issued
Array ( [id] => 13679471 [patent_doc_number] => 20160378472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Instruction and Logic for Predication and Implicit Destination [patent_app_type] => utility [patent_app_number] => 14/750940 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750940 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750940
Instruction and logic for predication and implicit destination Jun 24, 2015 Issued
Array ( [id] => 12039409 [patent_doc_number] => 09817642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Apparatus and method for efficient call/return emulation using a dual return stack buffer' [patent_app_type] => utility [patent_app_number] => 14/751052 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 18548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751052 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751052
Apparatus and method for efficient call/return emulation using a dual return stack buffer Jun 24, 2015 Issued
Array ( [id] => 12228916 [patent_doc_number] => 09916161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Instruction and logic for tracking fetch performance bottlenecks' [patent_app_type] => utility [patent_app_number] => 14/750535 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 23204 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750535
Instruction and logic for tracking fetch performance bottlenecks Jun 24, 2015 Issued
Array ( [id] => 11509122 [patent_doc_number] => 09600282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Endian-mode-independent memory access in a bi-endian-mode processor architecture' [patent_app_type] => utility [patent_app_number] => 14/724995 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8244 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724995
Endian-mode-independent memory access in a bi-endian-mode processor architecture May 28, 2015 Issued
Array ( [id] => 14523331 [patent_doc_number] => 10338926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Processor with conditional instructions [patent_app_type] => utility [patent_app_number] => 14/716245 [patent_app_country] => US [patent_app_date] => 2015-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6321 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14716245 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/716245
Processor with conditional instructions May 18, 2015 Issued
Array ( [id] => 15982131 [patent_doc_number] => 10671393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Techniques for facilitating cracking and fusion within a same instruction group [patent_app_type] => utility [patent_app_number] => 14/695594 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 19476 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695594 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/695594
Techniques for facilitating cracking and fusion within a same instruction group Apr 23, 2015 Issued
Array ( [id] => 11117025 [patent_doc_number] => 20160313999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'ENERGY EFFICIENT PROCESSOR CORE ARCHITECTURE FOR IMAGE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/694815 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11012 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694815
Energy efficient processor core architecture for image processor Apr 22, 2015 Issued
Array ( [id] => 11273012 [patent_doc_number] => 20160335558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'QUANTUM PROCESSOR WITH INSTANCE PROGRAMMABLE QUBIT CONNECTIVITY' [patent_app_type] => utility [patent_app_number] => 14/691268 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 21536 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14691268 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/691268
Quantum processor with instance programmable qubit connectivity Apr 19, 2015 Issued
Array ( [id] => 12046329 [patent_doc_number] => 09823932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Branch prediction' [patent_app_type] => utility [patent_app_number] => 14/690603 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3347 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14690603 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/690603
Branch prediction Apr 19, 2015 Issued
Array ( [id] => 11889855 [patent_doc_number] => 09760416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Multiprocessor messaging system' [patent_app_type] => utility [patent_app_number] => 14/689735 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2692 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14689735 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/689735
Multiprocessor messaging system Apr 16, 2015 Issued
Array ( [id] => 10746068 [patent_doc_number] => 20160092218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'Conditional Stop Instruction with Accurate Dependency Detection' [patent_app_type] => utility [patent_app_number] => 14/688043 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/688043
Conditional stop instruction with accurate dependency detection Apr 15, 2015 Issued
Array ( [id] => 11095012 [patent_doc_number] => 20160291980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'METHOD AND APPARATUS FOR A SUPERSCALAR PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/676461 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676461
Method and apparatus for a self-clocked, event triggered superscalar processor Mar 31, 2015 Issued
Array ( [id] => 11095011 [patent_doc_number] => 20160291979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'PARALLELIZED EXECUTION OF INSTRUCTION SEQUENCES' [patent_app_type] => utility [patent_app_number] => 14/673889 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8721 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673889 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673889
Parallelized execution of instruction sequences Mar 30, 2015 Issued
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