Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11095014 [patent_doc_number] => 20160291982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'PARALLELIZED EXECUTION OF INSTRUCTION SEQUENCES BASED ON PRE-MONITORING' [patent_app_type] => utility [patent_app_number] => 14/673884 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8719 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673884 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673884
Parallelized execution of instruction sequences based on pre-monitoring Mar 30, 2015 Issued
Array ( [id] => 11860812 [patent_doc_number] => 09740495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Implementing out of order processor instruction issue queue' [patent_app_type] => utility [patent_app_number] => 14/628188 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 5716 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628188
Implementing out of order processor instruction issue queue Feb 19, 2015 Issued
Array ( [id] => 11830638 [patent_doc_number] => 09727380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Global register protection in a multi-threaded processor' [patent_app_type] => utility [patent_app_number] => 14/625895 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6076 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14625895 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/625895
Global register protection in a multi-threaded processor Feb 18, 2015 Issued
Array ( [id] => 10357207 [patent_doc_number] => 20150242212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'MODELESS INSTRUCTION EXECUTION WITH 64/32-BIT ADDRESSING' [patent_app_type] => utility [patent_app_number] => 14/612090 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7807 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612090
Modeless instruction execution with 64/32-bit addressing Feb 1, 2015 Issued
Array ( [id] => 12011523 [patent_doc_number] => 09804841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Single instruction multiple data add processors, methods, systems, and instructions' [patent_app_type] => utility [patent_app_number] => 14/600846 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8556 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14600846 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/600846
Single instruction multiple data add processors, methods, systems, and instructions Jan 19, 2015 Issued
Array ( [id] => 10991585 [patent_doc_number] => 20160188530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX AND AN IMMEDIATE' [patent_app_type] => utility [patent_app_number] => 14/583644 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15518 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583644 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583644
Method and apparatus for performing a vector permute with an index and an immediate Dec 26, 2014 Issued
Array ( [id] => 10991388 [patent_doc_number] => 20160188333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD AND APPARATUS FOR COMPRESSING A MASK VALUE' [patent_app_type] => utility [patent_app_number] => 14/583647 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15260 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583647 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583647
METHOD AND APPARATUS FOR COMPRESSING A MASK VALUE Dec 26, 2014 Abandoned
Array ( [id] => 14330633 [patent_doc_number] => 10296334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Method and apparatus for performing a vector bit gather [patent_app_type] => utility [patent_app_number] => 14/583639 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 15336 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583639 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583639
Method and apparatus for performing a vector bit gather Dec 26, 2014 Issued
Array ( [id] => 10991587 [patent_doc_number] => 20160188532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE' [patent_app_type] => utility [patent_app_number] => 14/583636 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15167 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583636 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583636
Method and apparatus for performing a vector bit shuffle Dec 26, 2014 Issued
Array ( [id] => 10982608 [patent_doc_number] => 20160179552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INSTRUCTION AND LOGIC FOR A MATRIX SCHEDULER' [patent_app_type] => utility [patent_app_number] => 14/581101 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 24185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581101 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/581101
Instruction and logic for a matrix scheduler Dec 22, 2014 Issued
Array ( [id] => 11903412 [patent_doc_number] => 09772846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Instruction and logic for processing text strings' [patent_app_type] => utility [patent_app_number] => 14/576101 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11742 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 479 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576101 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576101
Instruction and logic for processing text strings Dec 17, 2014 Issued
Array ( [id] => 11738982 [patent_doc_number] => 09703564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Instruction and logic for processing text strings' [patent_app_type] => utility [patent_app_number] => 14/576124 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11714 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 452 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576124 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576124
Instruction and logic for processing text strings Dec 17, 2014 Issued
Array ( [id] => 11903413 [patent_doc_number] => 09772847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Instruction and logic for processing text strings' [patent_app_type] => utility [patent_app_number] => 14/576136 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11729 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 449 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576136 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576136
Instruction and logic for processing text strings Dec 17, 2014 Issued
Array ( [id] => 11860807 [patent_doc_number] => 09740490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Instruction and logic for processing text strings' [patent_app_type] => utility [patent_app_number] => 14/576147 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11713 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 494 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576147
Instruction and logic for processing text strings Dec 17, 2014 Issued
Array ( [id] => 13226545 [patent_doc_number] => 10127048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Architecture for long latency operations in emulated shared memory architectures [patent_app_type] => utility [patent_app_number] => 15/105583 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4077 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15105583 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/105583
Architecture for long latency operations in emulated shared memory architectures Dec 15, 2014 Issued
Array ( [id] => 10816133 [patent_doc_number] => 20160162294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'RECONFIGURABLE PROCESSORS AND METHODS FOR COLLECTING COMPUTER PROGRAM INSTRUCTION EXECUTION STATISTICS' [patent_app_type] => utility [patent_app_number] => 14/562742 [patent_app_country] => US [patent_app_date] => 2014-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562742 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562742
Reconfigurable processors and methods for collecting computer program instruction execution statistics Dec 6, 2014 Issued
Array ( [id] => 10293080 [patent_doc_number] => 20150178079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS' [patent_app_type] => utility [patent_app_number] => 14/562609 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11716 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562609 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562609
Instruction and logic for processing text strings Dec 4, 2014 Issued
Array ( [id] => 10293082 [patent_doc_number] => 20150178081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS' [patent_app_type] => utility [patent_app_number] => 14/562624 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11716 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562624 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562624
Instruction and logic for processing text strings Dec 4, 2014 Issued
Array ( [id] => 10293083 [patent_doc_number] => 20150178082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS' [patent_app_type] => utility [patent_app_number] => 14/562632 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11712 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562632
Instruction and logic for processing text strings Dec 4, 2014 Issued
Array ( [id] => 10293085 [patent_doc_number] => 20150178084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS' [patent_app_type] => utility [patent_app_number] => 14/562641 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11713 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562641 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562641
Instruction and logic for processing text strings Dec 4, 2014 Issued
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