Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10293084 [patent_doc_number] => 20150178083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS' [patent_app_type] => utility [patent_app_number] => 14/562637 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11713 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562637 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562637
Instruction and logic for processing text strings Dec 4, 2014 Issued
Array ( [id] => 10258078 [patent_doc_number] => 20150143075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'VECTOR GENERATE MASK INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/561815 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18585 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14561815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/561815
Vector generate mask instruction Dec 4, 2014 Issued
Array ( [id] => 11830592 [patent_doc_number] => 09727334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Vector exception code' [patent_app_type] => utility [patent_app_number] => 14/562132 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 18512 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562132 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562132
Vector exception code Dec 4, 2014 Issued
Array ( [id] => 10293081 [patent_doc_number] => 20150178080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS' [patent_app_type] => utility [patent_app_number] => 14/562618 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11738 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562618 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562618
Instruction and logic for processing text strings Dec 4, 2014 Issued
Array ( [id] => 13817593 [patent_doc_number] => 10185565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Method and apparatus for controlling register of reconfigurable processor, and method and apparatus for creating command for controlling register of reconfigurable processor [patent_app_type] => utility [patent_app_number] => 15/100452 [patent_app_country] => US [patent_app_date] => 2014-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5590 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15100452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/100452
Method and apparatus for controlling register of reconfigurable processor, and method and apparatus for creating command for controlling register of reconfigurable processor Nov 27, 2014 Issued
Array ( [id] => 9919178 [patent_doc_number] => 20150074383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/542631 [patent_app_country] => US [patent_app_date] => 2014-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18660 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542631 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542631
Vector galois field multiply sum and accumulate instruction Nov 15, 2014 Issued
Array ( [id] => 11563541 [patent_doc_number] => 09626129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Storage system' [patent_app_type] => utility [patent_app_number] => 14/536748 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14536748 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/536748
Storage system Nov 9, 2014 Issued
Array ( [id] => 11232642 [patent_doc_number] => 09459870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Data processor' [patent_app_type] => utility [patent_app_number] => 14/499334 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5839 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499334 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499334
Data processor Sep 28, 2014 Issued
Array ( [id] => 10976986 [patent_doc_number] => 20140380021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'PROCESSOR, MULTIPROCESSOR SYSTEM, COMPILER, SOFTWARE SYSTEM, MEMORY CONTROL SYSTEM, AND COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/479003 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10662 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479003 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479003
Processor, multiprocessor system, compiler, software system, memory control system, and computer system Sep 4, 2014 Issued
Array ( [id] => 10956234 [patent_doc_number] => 20140359255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'Coarse-Grained Data Processor Having Both Global and Direct Interconnects' [patent_app_type] => utility [patent_app_number] => 14/462858 [patent_app_country] => US [patent_app_date] => 2014-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 19136 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14462858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/462858
Coarse-Grained Data Processor Having Both Global and Direct Interconnects Aug 18, 2014 Abandoned
Array ( [id] => 11006034 [patent_doc_number] => 20160202983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'PROCESSOR SYSTEM AND METHOD BASED ON INSTRUCTION READ BUFFER' [patent_app_type] => utility [patent_app_number] => 14/913341 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 68548 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/913341
Processor system and method based on instruction read buffer Aug 17, 2014 Issued
Array ( [id] => 11013202 [patent_doc_number] => 20160210154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'HIGH PERFORMANCE PROCESSOR SYSTEM AND METHOD BASED ON GENERAL PURPOSE UNITS' [patent_app_type] => utility [patent_app_number] => 14/912726 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 46859 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14912726 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/912726
High performance processor system and method based on general purpose units Aug 17, 2014 Issued
Array ( [id] => 11006035 [patent_doc_number] => 20160202985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'Variable Length Instruction Processor System and Method' [patent_app_type] => utility [patent_app_number] => 14/913352 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 46524 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913352 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/913352
Variable length instruction processor system and method Aug 14, 2014 Issued
Array ( [id] => 11801245 [patent_doc_number] => 09542121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Memory device using extended interface commands' [patent_app_type] => utility [patent_app_number] => 14/459171 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459171 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459171
Memory device using extended interface commands Aug 12, 2014 Issued
Array ( [id] => 11359225 [patent_doc_number] => 09535877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Processing system with interspersed processors and communication elements having improved communication routing' [patent_app_type] => utility [patent_app_number] => 14/451900 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 21186 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14451900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/451900
Processing system with interspersed processors and communication elements having improved communication routing Aug 4, 2014 Issued
Array ( [id] => 12101105 [patent_doc_number] => 09858200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Configurable device interfaces' [patent_app_type] => utility [patent_app_number] => 14/450527 [patent_app_country] => US [patent_app_date] => 2014-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 40988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14450527 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/450527
Configurable device interfaces Aug 3, 2014 Issued
Array ( [id] => 16972299 [patent_doc_number] => 11068271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Zero cycle move using free list counts [patent_app_type] => utility [patent_app_number] => 14/444798 [patent_app_country] => US [patent_app_date] => 2014-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14444798 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/444798
Zero cycle move using free list counts Jul 27, 2014 Issued
Array ( [id] => 10221602 [patent_doc_number] => 20150106595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'PRIORITIZING INSTRUCTIONS BASED ON TYPE' [patent_app_type] => utility [patent_app_number] => 14/340932 [patent_app_country] => US [patent_app_date] => 2014-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340932 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340932
Prioritizing instructions based on type Jul 24, 2014 Issued
Array ( [id] => 10177541 [patent_doc_number] => 09207745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold' [patent_app_type] => utility [patent_app_number] => 14/340328 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340328 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340328
Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold Jul 23, 2014 Issued
Array ( [id] => 10603150 [patent_doc_number] => 09323716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Hierarchical reconfigurable computer architecture' [patent_app_type] => utility [patent_app_number] => 14/329226 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8231 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329226 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329226
Hierarchical reconfigurable computer architecture Jul 10, 2014 Issued
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