
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10293084
[patent_doc_number] => 20150178083
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[patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS'
[patent_app_type] => utility
[patent_app_number] => 14/562637
[patent_app_country] => US
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Array
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[patent_doc_number] => 20150143075
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[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'VECTOR GENERATE MASK INSTRUCTION'
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Array
(
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[patent_issue_date] => 2017-08-08
[patent_title] => 'Vector exception code'
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Array
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[patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS'
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Array
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[patent_doc_number] => 10185565
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[patent_kind] => B2
[patent_issue_date] => 2019-01-22
[patent_title] => Method and apparatus for controlling register of reconfigurable processor, and method and apparatus for creating command for controlling register of reconfigurable processor
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[patent_app_number] => 15/100452
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/100452 | Method and apparatus for controlling register of reconfigurable processor, and method and apparatus for creating command for controlling register of reconfigurable processor | Nov 27, 2014 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/536748 | Storage system | Nov 9, 2014 | Issued |
Array
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[id] => 11232642
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/499334 | Data processor | Sep 28, 2014 | Issued |
Array
(
[id] => 10976986
[patent_doc_number] => 20140380021
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[patent_issue_date] => 2014-12-25
[patent_title] => 'PROCESSOR, MULTIPROCESSOR SYSTEM, COMPILER, SOFTWARE SYSTEM, MEMORY CONTROL SYSTEM, AND COMPUTER SYSTEM'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/462858 | Coarse-Grained Data Processor Having Both Global and Direct Interconnects | Aug 18, 2014 | Abandoned |
Array
(
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[patent_title] => 'PROCESSOR SYSTEM AND METHOD BASED ON INSTRUCTION READ BUFFER'
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Array
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Array
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