Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11193223 [patent_doc_number] => 09424039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Instruction for implementing vector loops of iterations having an iteration dependent condition' [patent_app_type] => utility [patent_app_number] => 14/327527 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 17444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327527 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/327527
Instruction for implementing vector loops of iterations having an iteration dependent condition Jul 8, 2014 Issued
Array ( [id] => 11791327 [patent_doc_number] => 09400963 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-26 [patent_title] => 'Task prioritization based on users\' interest' [patent_app_type] => utility [patent_app_number] => 14/325478 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5280 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325478 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325478
Task prioritization based on users' interest Jul 7, 2014 Issued
Array ( [id] => 9794906 [patent_doc_number] => 20150006850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'PROCESSOR WITH HETEROGENEOUS CLUSTERED ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/314282 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314282 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314282
PROCESSOR WITH HETEROGENEOUS CLUSTERED ARCHITECTURE Jun 24, 2014 Abandoned
Array ( [id] => 10485543 [patent_doc_number] => 20150370562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'EFFICIENT CONDITIONAL INSTRUCTION HAVING COMPANION LOAD PREDICATE BITS INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/311225 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14311225 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/311225
Efficient conditional instruction having companion load predicate bits instruction Jun 19, 2014 Issued
Array ( [id] => 10485541 [patent_doc_number] => 20150370561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'SKIP INSTRUCTION TO SKIP A NUMBER OF INSTRUCTIONS ON A PREDICATE' [patent_app_type] => utility [patent_app_number] => 14/311222 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14311222 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/311222
Skip instruction to skip a number of instructions on a predicate Jun 19, 2014 Issued
Array ( [id] => 10907491 [patent_doc_number] => 20140310505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'COMPRESSED INSTRUCTION FORMAT' [patent_app_type] => utility [patent_app_number] => 14/307468 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6590 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14307468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/307468
Compressed instruction format Jun 16, 2014 Issued
Array ( [id] => 10478188 [patent_doc_number] => 20150363205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'IMPLEMENTING OUT OF ORDER PROCESSOR INSTRUCTION ISSUE QUEUE' [patent_app_type] => utility [patent_app_number] => 14/306328 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 5721 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14306328 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/306328
Implementing out of order processor instruction issue queue Jun 16, 2014 Issued
Array ( [id] => 10907491 [patent_doc_number] => 20140310505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'COMPRESSED INSTRUCTION FORMAT' [patent_app_type] => utility [patent_app_number] => 14/307468 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6590 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14307468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/307468
Compressed instruction format Jun 16, 2014 Issued
Array ( [id] => 10907491 [patent_doc_number] => 20140310505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'COMPRESSED INSTRUCTION FORMAT' [patent_app_type] => utility [patent_app_number] => 14/307468 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6590 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14307468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/307468
Compressed instruction format Jun 16, 2014 Issued
Array ( [id] => 10644288 [patent_doc_number] => 09361160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Virtualization across physical partitions of a multi-core processor (MCP)' [patent_app_type] => utility [patent_app_number] => 14/281062 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281062 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/281062
Virtualization across physical partitions of a multi-core processor (MCP) May 18, 2014 Issued
Array ( [id] => 10124188 [patent_doc_number] => 09158547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Methods and apparatus for scalable array processor interrupt detection and response' [patent_app_type] => utility [patent_app_number] => 14/264263 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 13655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264263 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264263
Methods and apparatus for scalable array processor interrupt detection and response Apr 28, 2014 Issued
Array ( [id] => 10065624 [patent_doc_number] => 09104470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Task processor' [patent_app_type] => utility [patent_app_number] => 14/243801 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 23134 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243801 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/243801
Task processor Apr 1, 2014 Issued
Array ( [id] => 10948546 [patent_doc_number] => 20140351565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT INFLATE AND DEFLATE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/223741 [patent_app_country] => US [patent_app_date] => 2014-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 392 [patent_figures_cnt] => 392 [patent_no_of_words] => 81559 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223741 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/223741
SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT INFLATE AND DEFLATE OPERATIONS Mar 23, 2014 Abandoned
Array ( [id] => 10363290 [patent_doc_number] => 20150248295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'NUMERICAL STALL ANALYSIS OF CPU PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/195783 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5216 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195783 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/195783
NUMERICAL STALL ANALYSIS OF CPU PERFORMANCE Mar 2, 2014 Abandoned
Array ( [id] => 10357208 [patent_doc_number] => 20150242213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'SYSTEM AND METHOD FOR MODIFICATION OF CODED INSTRUCTIONS IN READ-ONLY MEMORY USING ONE-TIME PROGRAMMABLE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/187272 [patent_app_country] => US [patent_app_date] => 2014-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6920 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187272 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187272
SYSTEM AND METHOD FOR MODIFICATION OF CODED INSTRUCTIONS IN READ-ONLY MEMORY USING ONE-TIME PROGRAMMABLE MEMORY Feb 22, 2014 Abandoned
Array ( [id] => 11458880 [patent_doc_number] => 20170052786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'RECONFIGURABLE PROCESSOR AND CONDITIONAL EXECUTION METHOD FOR THE SAME' [patent_app_type] => utility [patent_app_number] => 15/119716 [patent_app_country] => US [patent_app_date] => 2014-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4897 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15119716 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/119716
Reconfigurable processor and conditional execution method for the same Feb 19, 2014 Issued
Array ( [id] => 10342363 [patent_doc_number] => 20150227368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'Completion Time Determination for Vector Instructions' [patent_app_type] => utility [patent_app_number] => 14/177378 [patent_app_country] => US [patent_app_date] => 2014-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/177378
Completion time determination for vector instructions Feb 10, 2014 Issued
Array ( [id] => 11359048 [patent_doc_number] => 09535701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Efficient use of branch delay slots and branch prediction in pipelined computer architectures' [patent_app_type] => utility [patent_app_number] => 14/167973 [patent_app_country] => US [patent_app_date] => 2014-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10691 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14167973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/167973
Efficient use of branch delay slots and branch prediction in pipelined computer architectures Jan 28, 2014 Issued
Array ( [id] => 10327816 [patent_doc_number] => 20150212820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'PROCESSOR LOOP BUFFER' [patent_app_type] => utility [patent_app_number] => 14/164633 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164633 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/164633
Processor loop buffer Jan 26, 2014 Issued
Array ( [id] => 10575826 [patent_doc_number] => 09298467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Switch statement prediction' [patent_app_type] => utility [patent_app_number] => 14/153188 [patent_app_country] => US [patent_app_date] => 2014-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14153188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/153188
Switch statement prediction Jan 12, 2014 Issued
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