Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10065580 [patent_doc_number] => 09104425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Apparatus and method for handling exception events' [patent_app_type] => utility [patent_app_number] => 14/149141 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10244 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149141 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/149141
Apparatus and method for handling exception events Jan 6, 2014 Issued
Array ( [id] => 11482227 [patent_doc_number] => 09588773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Software based application specific integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/149009 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 9300 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/149009
Software based application specific integrated circuit Jan 6, 2014 Issued
Array ( [id] => 10556141 [patent_doc_number] => 09280341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Data processing device' [patent_app_type] => utility [patent_app_number] => 14/144822 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8227 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144822 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144822
Data processing device Dec 30, 2013 Issued
Array ( [id] => 13820839 [patent_doc_number] => 10187208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => RSA algorithm acceleration processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 15/102637 [patent_app_country] => US [patent_app_date] => 2013-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14079 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15102637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/102637
RSA algorithm acceleration processors, methods, systems, and instructions Dec 27, 2013 Issued
Array ( [id] => 11117027 [patent_doc_number] => 20160314000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'INSTRUCTION AND LOGIC FOR IDENTIFYING INSTRUCTIONS FOR RETIREMENT IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/103765 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 21047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15103765 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/103765
Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor Dec 22, 2013 Issued
Array ( [id] => 9398427 [patent_doc_number] => 20140095833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'Prefix Computer Instruction for Compatibly Extending Instruction Functionality' [patent_app_type] => utility [patent_app_number] => 14/100184 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21489 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100184 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100184
Prefix computer instruction for compatibly extending instruction functionality Dec 8, 2013 Issued
Array ( [id] => 9424120 [patent_doc_number] => 20140108771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'Using Register Last Use Information to Perform Decode Time Computer Instruction Optimization' [patent_app_type] => utility [patent_app_number] => 14/099313 [patent_app_country] => US [patent_app_date] => 2013-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22529 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099313 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/099313
Using register last use information to perform decode time computer instruction optimization Dec 5, 2013 Issued
Array ( [id] => 10873215 [patent_doc_number] => 08898435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Optimizing system throughput by automatically altering thread co-execution based on operating system directives' [patent_app_type] => utility [patent_app_number] => 14/093340 [patent_app_country] => US [patent_app_date] => 2013-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7298 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093340
Optimizing system throughput by automatically altering thread co-execution based on operating system directives Nov 28, 2013 Issued
Array ( [id] => 9807898 [patent_doc_number] => 20150019843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'METHOD AND APPARATUS FOR SELECTIVE RENAMING IN A MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/091340 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9615 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/091340
Method and apparatus for selective renaming in a microprocessor Nov 26, 2013 Issued
Array ( [id] => 9513222 [patent_doc_number] => 20140149714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'RECONFIGURABLE PROCESSOR FOR PARALLEL PROCESSING AND OPERATION METHOD OF THE RECONFIGURABLE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/092060 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5084 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14092060 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/092060
Reconfigurable processor for parallel processing and operation method of the reconfigurable processor Nov 26, 2013 Issued
Array ( [id] => 11238974 [patent_doc_number] => 09465619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-11 [patent_title] => 'Systems and methods for shared pipeline architectures having minimalized delay' [patent_app_type] => utility [patent_app_number] => 14/090698 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5685 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090698
Systems and methods for shared pipeline architectures having minimalized delay Nov 25, 2013 Issued
Array ( [id] => 10228260 [patent_doc_number] => 20150113253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'SELECTIVELY COMPRESSED MICROCODE' [patent_app_type] => utility [patent_app_number] => 14/088565 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088565 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088565
Selectively compressed microcode Nov 24, 2013 Issued
Array ( [id] => 11764273 [patent_doc_number] => 09372696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Microprocessor with compressed and uncompressed microcode memories' [patent_app_type] => utility [patent_app_number] => 14/088620 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10853 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088620 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088620
Microprocessor with compressed and uncompressed microcode memories Nov 24, 2013 Issued
Array ( [id] => 10258081 [patent_doc_number] => 20150143078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'VECTOR PROCESSING ENGINES (VPEs) EMPLOYING A TAPPED-DELAY LINE(S) FOR PROVIDING PRECISION FILTER VECTOR PROCESSING OPERATIONS WITH REDUCED SAMPLE RE-FETCHING AND POWER CONSUMPTION, AND RELATED VECTOR PROCESSOR SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/082075 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 55925 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082075
Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods Nov 14, 2013 Issued
Array ( [id] => 11584727 [patent_doc_number] => 09639369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Split register file for operands of different sizes' [patent_app_type] => utility [patent_app_number] => 14/076660 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076660 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076660
Split register file for operands of different sizes Nov 10, 2013 Issued
Array ( [id] => 10589514 [patent_doc_number] => 09311129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Methods and systems for converting a related group of physical machines to virtual machines' [patent_app_type] => utility [patent_app_number] => 14/050317 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050317 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050317
Methods and systems for converting a related group of physical machines to virtual machines Oct 8, 2013 Issued
Array ( [id] => 9308444 [patent_doc_number] => 20140047118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'OPTIMIZING RESOURCE CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 14/042026 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042026
Optimizing resource configurations Sep 29, 2013 Issued
Array ( [id] => 10885770 [patent_doc_number] => 08910174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Storage system' [patent_app_type] => utility [patent_app_number] => 14/023509 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11284 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023509
Storage system Sep 10, 2013 Issued
Array ( [id] => 9745684 [patent_doc_number] => 20140281403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'CHAINING BETWEEN EXPOSED VECTOR PIPELINES' [patent_app_type] => utility [patent_app_number] => 13/966408 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9260 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966408 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966408
Chaining between exposed vector pipelines Aug 13, 2013 Issued
Array ( [id] => 9398351 [patent_doc_number] => 20140095757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP WITH PROGRAMMABLE INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 13/966028 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 18289 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966028 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966028
Microcontroller programmable system on a chip with programmable interconnect Aug 12, 2013 Issued
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