Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10651060 [patent_doc_number] => 09367311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Multi-core processor system, synchronization control system, synchronization control apparatus, information generating method, and computer product' [patent_app_type] => utility [patent_app_number] => 13/765338 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10574 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765338 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765338
Multi-core processor system, synchronization control system, synchronization control apparatus, information generating method, and computer product Feb 11, 2013 Issued
Array ( [id] => 9618222 [patent_doc_number] => 20140208079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/748510 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748510 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748510
Vector Galois Field Multiply Sum and Accumulate instruction Jan 22, 2013 Issued
Array ( [id] => 9618229 [patent_doc_number] => 20140208086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'VECTOR EXCEPTION CODE' [patent_app_type] => utility [patent_app_number] => 13/748504 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748504 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748504
Vector exception code Jan 22, 2013 Issued
Array ( [id] => 8843540 [patent_doc_number] => 20130139168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'Scaleable Status Tracking Of Multiple Assist Hardware Threads' [patent_app_type] => utility [patent_app_number] => 13/748540 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9118 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748540 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748540
Scaleable status tracking of multiple assist hardware threads Jan 22, 2013 Issued
Array ( [id] => 11910124 [patent_doc_number] => 09778932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Vector generate mask instruction' [patent_app_type] => utility [patent_app_number] => 13/748538 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 18563 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748538 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748538
Vector generate mask instruction Jan 22, 2013 Issued
Array ( [id] => 9109883 [patent_doc_number] => 20130283015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'EXPRESSING PARALLEL EXECUTION RELATIONSHIPS IN A SEQUENTIAL PROGRAMMING LANGUAGE' [patent_app_type] => utility [patent_app_number] => 13/735438 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735438
Expressing parallel execution relationships in a sequential programming language Jan 6, 2013 Issued
Array ( [id] => 9571600 [patent_doc_number] => 20140189313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD' [patent_app_type] => utility [patent_app_number] => 13/730407 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730407 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730407
Queued instruction re-dispatch after runahead Dec 27, 2012 Issued
Array ( [id] => 9680466 [patent_doc_number] => 08819394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Instruction and logic for processing text strings' [patent_app_type] => utility [patent_app_number] => 13/721725 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11744 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721725 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721725
Instruction and logic for processing text strings Dec 19, 2012 Issued
Array ( [id] => 11213686 [patent_doc_number] => 09442721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Method and system to provide user-level multithreading' [patent_app_type] => utility [patent_app_number] => 13/722481 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12336 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722481
Method and system to provide user-level multithreading Dec 19, 2012 Issued
Array ( [id] => 8823782 [patent_doc_number] => 20130124827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS' [patent_app_type] => utility [patent_app_number] => 13/721819 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11762 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721819 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721819
Instruction and logic for processing text strings Dec 19, 2012 Issued
Array ( [id] => 10834931 [patent_doc_number] => 08863127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Virtual machine utility computing method and system' [patent_app_type] => utility [patent_app_number] => 13/717475 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13717475 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/717475
Virtual machine utility computing method and system Dec 16, 2012 Issued
Array ( [id] => 10550231 [patent_doc_number] => 09274856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Improving processor performance for instruction sequences that include barrier instructions' [patent_app_type] => utility [patent_app_number] => 13/687306 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11932 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13687306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/687306
Improving processor performance for instruction sequences that include barrier instructions Nov 27, 2012 Issued
Array ( [id] => 8735486 [patent_doc_number] => 20130081055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'TASK PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/682633 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 23147 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13682633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/682633
Task processor Nov 19, 2012 Issued
Array ( [id] => 10556313 [patent_doc_number] => 09280513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-08 [patent_title] => 'Matrix processor proxy systems and methods' [patent_app_type] => utility [patent_app_number] => 13/633848 [patent_app_country] => US [patent_app_date] => 2012-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 17635 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13633848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/633848
Matrix processor proxy systems and methods Oct 1, 2012 Issued
Array ( [id] => 11791025 [patent_doc_number] => 09400650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-26 [patent_title] => 'Read and write masks update instruction for vectorization of recursive computations over interdependent data' [patent_app_type] => utility [patent_app_number] => 13/630247 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 11297 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13630247 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/630247
Read and write masks update instruction for vectorization of recursive computations over interdependent data Sep 27, 2012 Issued
Array ( [id] => 11465656 [patent_doc_number] => 09582287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions' [patent_app_type] => utility [patent_app_number] => 13/629460 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 17651 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13629460 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/629460
Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions Sep 26, 2012 Issued
Array ( [id] => 9023435 [patent_doc_number] => 08533432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Cache and/or socket sensitive multi-processor cores breadth-first traversal' [patent_app_type] => utility [patent_app_number] => 13/629087 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4920 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13629087 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/629087
Cache and/or socket sensitive multi-processor cores breadth-first traversal Sep 26, 2012 Issued
Array ( [id] => 8588452 [patent_doc_number] => 20130007273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'OPTIMIZING RESOURCE CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 13/615175 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13804 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615175 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/615175
Optimizing resource configurations Sep 12, 2012 Issued
Array ( [id] => 8568700 [patent_doc_number] => 20120331271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'COMPRESSED INSTRUCTION FORMAT' [patent_app_type] => utility [patent_app_number] => 13/607594 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6542 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607594 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607594
Compressed instruction format Sep 6, 2012 Issued
Array ( [id] => 8524758 [patent_doc_number] => 20120324166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'COMPUTER-IMPLEMENTED METHOD OF PROCESSING RESOURCE MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/599102 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4798 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13599102 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/599102
Computer-implemented method of processing resource management Aug 29, 2012 Issued
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