Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20317186 [patent_doc_number] => 12455737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Neural network compute tile [patent_app_type] => utility [patent_app_number] => 18/505743 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4787 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505743
Neural network compute tile Nov 8, 2023 Issued
Array ( [id] => 20317186 [patent_doc_number] => 12455737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Neural network compute tile [patent_app_type] => utility [patent_app_number] => 18/505743 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4787 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505743
Neural network compute tile Nov 8, 2023 Issued
Array ( [id] => 19251005 [patent_doc_number] => 20240201995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => PROCESSOR AND METHOD FOR ASSIGNING CONFIG ID FOR CORE INCLUDED IN THE SAME [patent_app_type] => utility [patent_app_number] => 18/495645 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18495645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/495645
Processor and method for assigning config ID for core included in the same Oct 25, 2023 Issued
Array ( [id] => 18974008 [patent_doc_number] => 20240054100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS [patent_app_type] => utility [patent_app_number] => 18/383311 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383311
Method of notifying a process or programmable atomic operation traps Oct 23, 2023 Issued
Array ( [id] => 18974008 [patent_doc_number] => 20240054100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS [patent_app_type] => utility [patent_app_number] => 18/383311 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383311
Method of notifying a process or programmable atomic operation traps Oct 23, 2023 Issued
Array ( [id] => 19885625 [patent_doc_number] => 12271339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Instruction format and instruction set architecture for tensor streaming processor [patent_app_type] => utility [patent_app_number] => 18/483026 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 131 [patent_no_of_words] => 11858 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483026 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483026
Instruction format and instruction set architecture for tensor streaming processor Oct 8, 2023 Issued
Array ( [id] => 19022041 [patent_doc_number] => 20240078212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => General-Purpose Systolic Array [patent_app_type] => utility [patent_app_number] => 18/376494 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376494 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376494
General-purpose systolic array Oct 3, 2023 Issued
Array ( [id] => 18998153 [patent_doc_number] => 11915001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-27 [patent_title] => Neural processor and method for fetching instructions thereof [patent_app_type] => utility [patent_app_number] => 18/477457 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 22609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/477457
Neural processor and method for fetching instructions thereof Sep 27, 2023 Issued
Array ( [id] => 19956724 [patent_doc_number] => 12327139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Apparatus for accelerating neural networks [patent_app_type] => utility [patent_app_number] => 18/373682 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 3688 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373682 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373682
Apparatus for accelerating neural networks Sep 26, 2023 Issued
Array ( [id] => 19036379 [patent_doc_number] => 20240086194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS [patent_app_type] => utility [patent_app_number] => 18/473088 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/473088
Instruction and logic for tracking fetch performance bottlenecks Sep 21, 2023 Issued
Array ( [id] => 19114806 [patent_doc_number] => 20240126556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => Vector Instruction Cracking After Scalar Dispatch [patent_app_type] => utility [patent_app_number] => 18/469008 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469008
Vector instruction cracking after scalar dispatch Sep 17, 2023 Issued
Array ( [id] => 19911857 [patent_doc_number] => 12288068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Instruction simulation device and method thereof [patent_app_type] => utility [patent_app_number] => 18/465189 [patent_app_country] => US [patent_app_date] => 2023-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10604 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18465189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/465189
Instruction simulation device and method thereof Sep 11, 2023 Issued
Array ( [id] => 19005848 [patent_doc_number] => 20240069919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CONTROL SYSTEM AND METHOD OF MACHINE AND HOST COMPUTER [patent_app_type] => utility [patent_app_number] => 18/463961 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/463961
Control system and method of machine and host computer Sep 7, 2023 Issued
Array ( [id] => 20331612 [patent_doc_number] => 12461889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Intelligent graph execution and orchestration engine for a reconfigurable data processor [patent_app_type] => utility [patent_app_number] => 18/243994 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 18336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/243994
Intelligent graph execution and orchestration engine for a reconfigurable data processor Sep 7, 2023 Issued
Array ( [id] => 20331612 [patent_doc_number] => 12461889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Intelligent graph execution and orchestration engine for a reconfigurable data processor [patent_app_type] => utility [patent_app_number] => 18/243994 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 18336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/243994
Intelligent graph execution and orchestration engine for a reconfigurable data processor Sep 7, 2023 Issued
Array ( [id] => 19005848 [patent_doc_number] => 20240069919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CONTROL SYSTEM AND METHOD OF MACHINE AND HOST COMPUTER [patent_app_type] => utility [patent_app_number] => 18/463961 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/463961
Control system and method of machine and host computer Sep 7, 2023 Issued
Array ( [id] => 20331612 [patent_doc_number] => 12461889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Intelligent graph execution and orchestration engine for a reconfigurable data processor [patent_app_type] => utility [patent_app_number] => 18/243994 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 18336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/243994
Intelligent graph execution and orchestration engine for a reconfigurable data processor Sep 7, 2023 Issued
Array ( [id] => 19719359 [patent_doc_number] => 12204898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Interruptible and restartable matrix multiplication instructions, processors, methods, and systems [patent_app_type] => utility [patent_app_number] => 18/240287 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 19291 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240287
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems Aug 29, 2023 Issued
Array ( [id] => 18989837 [patent_doc_number] => 20240061806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => MULTI-CORE PROCESSING AND MEMORY ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 18/239040 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239040
Multi-core processing and memory arrangement Aug 27, 2023 Issued
Array ( [id] => 19427171 [patent_doc_number] => 12086594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Vector friendly instruction format and execution thereof [patent_app_type] => utility [patent_app_number] => 18/239106 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 78 [patent_no_of_words] => 31681 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239106
Vector friendly instruction format and execution thereof Aug 27, 2023 Issued
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