Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9826017 [patent_doc_number] => 08935513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Processor performance improvement for instruction sequences that include barrier instructions' [patent_app_type] => utility [patent_app_number] => 13/369029 [patent_app_country] => US [patent_app_date] => 2012-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11904 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369029 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369029
Processor performance improvement for instruction sequences that include barrier instructions Feb 7, 2012 Issued
Array ( [id] => 11801311 [patent_doc_number] => 09542187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Guest instruction block with near branching and far branching sequence construction to native instruction block' [patent_app_type] => utility [patent_app_number] => 13/359817 [patent_app_country] => US [patent_app_date] => 2012-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11397 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13359817 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/359817
Guest instruction block with near branching and far branching sequence construction to native instruction block Jan 26, 2012 Issued
Array ( [id] => 11523410 [patent_doc_number] => 09606808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Method and system for resolving thread divergences' [patent_app_type] => utility [patent_app_number] => 13/348544 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9146 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348544 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348544
Method and system for resolving thread divergences Jan 10, 2012 Issued
Array ( [id] => 8162631 [patent_doc_number] => 20120102301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'PREDICATE COUNT AND SEGMENT COUNT INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/343619 [patent_app_country] => US [patent_app_date] => 2012-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 39557 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102301.pdf [firstpage_image] =>[orig_patent_app_number] => 13343619 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343619
Predicate count and segment count instructions for processing vectors Jan 3, 2012 Issued
Array ( [id] => 11232638 [patent_doc_number] => 09459866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Vector frequency compress instruction' [patent_app_type] => utility [patent_app_number] => 13/993058 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 16623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993058 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993058
Vector frequency compress instruction Dec 29, 2011 Issued
Array ( [id] => 9213914 [patent_doc_number] => 20140013091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'CAUSING AN INTERRUPT BASED ON EVENT COUNT' [patent_app_type] => utility [patent_app_number] => 13/991878 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5153 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13991878 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/991878
Causing an interrupt based on event count Dec 28, 2011 Issued
Array ( [id] => 9465374 [patent_doc_number] => 20140129801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING DELTA ENCODING ON PACKED DATA ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/976427 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976427
Systems, apparatuses, and methods for performing delta encoding on packed data elements Dec 27, 2011 Issued
Array ( [id] => 9200353 [patent_doc_number] => 20130339668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING DELTA DECODING ON PACKED DATA ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/997662 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16769 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997662
Systems, apparatuses, and methods for performing delta decoding on packed data elements Dec 27, 2011 Issued
Array ( [id] => 10962717 [patent_doc_number] => 20140365747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL PARTIAL SUM IN RESPONSE TO A SINGLE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/977612 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977612 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977612
Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction Dec 22, 2011 Issued
Array ( [id] => 11430961 [patent_doc_number] => 09569278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Asymmetric performance multicore architecture with same instruction set architecture' [patent_app_type] => utility [patent_app_number] => 13/335257 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335257 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/335257
Asymmetric performance multicore architecture with same instruction set architecture Dec 21, 2011 Issued
Array ( [id] => 11563602 [patent_doc_number] => 09626191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Shaped register file reads' [patent_app_type] => utility [patent_app_number] => 13/335868 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335868 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/335868
Shaped register file reads Dec 21, 2011 Issued
Array ( [id] => 10854147 [patent_doc_number] => 08880857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor' [patent_app_type] => utility [patent_app_number] => 13/333572 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 36286 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333572 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333572
Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor Dec 20, 2011 Issued
Array ( [id] => 9986454 [patent_doc_number] => 09032189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Efficient conditional ALU instruction in read-port limited register file microprocessor' [patent_app_type] => utility [patent_app_number] => 13/333520 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 36402 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333520
Efficient conditional ALU instruction in read-port limited register file microprocessor Dec 20, 2011 Issued
Array ( [id] => 8267350 [patent_doc_number] => 20120166776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'METHOD, SYSTEM, AND COMPUTER PROGRAM FOR ANALYZING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/332436 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4689 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332436
Method, system, and computer program for analyzing program Dec 20, 2011 Issued
Array ( [id] => 8213881 [patent_doc_number] => 20120131310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Methods And Apparatus For Independent Processor Node Operations In A SIMD Array Processor' [patent_app_type] => utility [patent_app_number] => 13/332482 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131310.pdf [firstpage_image] =>[orig_patent_app_number] => 13332482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332482
Methods and apparatus for independent processor node operations in a SIMD array processor Dec 20, 2011 Issued
Array ( [id] => 9940712 [patent_doc_number] => 08990544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Method and apparatus for using a previous column pointer to read entries in an array of a processor' [patent_app_type] => utility [patent_app_number] => 13/333125 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 4396 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333125 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333125
Method and apparatus for using a previous column pointer to read entries in an array of a processor Dec 20, 2011 Issued
Array ( [id] => 9986451 [patent_doc_number] => 09032187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Instruction execution' [patent_app_type] => utility [patent_app_number] => 13/331716 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3652 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331716
Instruction execution Dec 19, 2011 Issued
Array ( [id] => 8568705 [patent_doc_number] => 20120331276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'Instruction Execution' [patent_app_type] => utility [patent_app_number] => 13/331828 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4088 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331828
Instruction execution Dec 19, 2011 Issued
Array ( [id] => 8097857 [patent_doc_number] => 20120084533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'Efficient Parallel Floating Point Exception Handling In A Processor' [patent_app_type] => utility [patent_app_number] => 13/325559 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9001 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084533.pdf [firstpage_image] =>[orig_patent_app_number] => 13325559 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/325559
Efficient parallel floating point exception handling in a processor Dec 13, 2011 Issued
Array ( [id] => 10623489 [patent_doc_number] => 09342432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Hardware performance-monitoring facility usage after context swaps' [patent_app_type] => utility [patent_app_number] => 13/313557 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3172 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/313557
Hardware performance-monitoring facility usage after context swaps Dec 6, 2011 Issued
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