Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11193227 [patent_doc_number] => 09424042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'System, apparatus and method for translating vector instructions' [patent_app_type] => utility [patent_app_number] => 13/993603 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993603
System, apparatus and method for translating vector instructions Dec 5, 2011 Issued
Array ( [id] => 8337341 [patent_doc_number] => 20120204013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT ARITHMETIC OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/310508 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 385 [patent_figures_cnt] => 385 [patent_no_of_words] => 81782 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310508 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310508
SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT ARITHMETIC OPERATIONS Dec 1, 2011 Abandoned
Array ( [id] => 8985095 [patent_doc_number] => 08516225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Central processing unit and microcontroller' [patent_app_type] => utility [patent_app_number] => 13/378482 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5393 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13378482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/378482
Central processing unit and microcontroller Nov 21, 2011 Issued
Array ( [id] => 8741128 [patent_doc_number] => 08412914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Macroscalar processor architecture' [patent_app_type] => utility [patent_app_number] => 13/298739 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 95 [patent_no_of_words] => 38450 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298739 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298739
Macroscalar processor architecture Nov 16, 2011 Issued
Array ( [id] => 9257745 [patent_doc_number] => 08621186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Obfuscated hardware multi-threading' [patent_app_type] => utility [patent_app_number] => 13/883937 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5144 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13883937 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/883937
Obfuscated hardware multi-threading Nov 13, 2011 Issued
Array ( [id] => 8823781 [patent_doc_number] => 20130124826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Optimizing System Throughput By Automatically Altering Thread Co-Execution Based On Operating System Directives' [patent_app_type] => utility [patent_app_number] => 13/294244 [patent_app_country] => US [patent_app_date] => 2011-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7263 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13294244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/294244
Optimizing system throughput by automatically altering thread co-execution based on operating system directives Nov 10, 2011 Issued
Array ( [id] => 8823784 [patent_doc_number] => 20130124829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'REDUCING POWER CONSUMPTION AND RESOURCE UTILIZATION DURING MISS LOOKAHEAD' [patent_app_type] => utility [patent_app_number] => 13/293733 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5691 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13293733 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/293733
Reducing power consumption and resource utilization during miss lookahead Nov 9, 2011 Issued
Array ( [id] => 8757034 [patent_doc_number] => 20130091339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'SIMD Memory Circuit And Methodology To Support Upsampling, Downsampling And Transposition' [patent_app_type] => utility [patent_app_number] => 13/253754 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10082 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13253754 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/253754
SIMD memory circuit and methodology to support upsampling, downsampling and transposition Oct 4, 2011 Issued
Array ( [id] => 8746645 [patent_doc_number] => 20130086362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand First-Use Information' [patent_app_type] => utility [patent_app_number] => 13/251426 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21783 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251426 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251426
Prefix computer instruction for compatibily extending instruction functionality Oct 2, 2011 Issued
Array ( [id] => 8746651 [patent_doc_number] => 20130086368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Using Register Last Use Infomation to Perform Decode-Time Computer Instruction Optimization' [patent_app_type] => utility [patent_app_number] => 13/251486 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22426 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251486 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251486
Using register last use infomation to perform decode-time computer instruction optimization Oct 2, 2011 Issued
Array ( [id] => 8746644 [patent_doc_number] => 20130086361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Scalable Decode-Time Instruction Sequence Optimization of Dependent Instructions' [patent_app_type] => utility [patent_app_number] => 13/251409 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13928 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251409 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251409
Scalable decode-time instruction sequence optimization of dependent instructions Oct 2, 2011 Issued
Array ( [id] => 8746643 [patent_doc_number] => 20130086360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'FIFO Load Instruction' [patent_app_type] => utility [patent_app_number] => 13/249284 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5597 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13249284 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/249284
FIFO load instruction Sep 29, 2011 Issued
Array ( [id] => 9992617 [patent_doc_number] => 09037838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-19 [patent_title] => 'Multiprocessor messaging system' [patent_app_type] => utility [patent_app_number] => 13/251151 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2652 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251151 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251151
Multiprocessor messaging system Sep 29, 2011 Issued
Array ( [id] => 12495642 [patent_doc_number] => 09996499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Scalable and programmable processor comprising multiple cooperating processor units [patent_app_type] => utility [patent_app_number] => 13/248869 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13248869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/248869
Scalable and programmable processor comprising multiple cooperating processor units Sep 28, 2011 Issued
Array ( [id] => 8619340 [patent_doc_number] => 20130024652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'Scalable Processing Unit' [patent_app_type] => utility [patent_app_number] => 13/236822 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236822 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236822
Scalable processing unit Sep 19, 2011 Issued
Array ( [id] => 14034397 [patent_doc_number] => 10228949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Single cycle multi-branch prediction including shadow cache for early far branch prediction [patent_app_type] => utility [patent_app_number] => 13/824013 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4614 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13824013 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/824013
Single cycle multi-branch prediction including shadow cache for early far branch prediction Sep 15, 2011 Issued
Array ( [id] => 11889811 [patent_doc_number] => 09760372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Parallel processing in plural processors with result register each performing associative operation on respective column data' [patent_app_type] => utility [patent_app_number] => 13/224090 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4751 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224090 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224090
Parallel processing in plural processors with result register each performing associative operation on respective column data Aug 31, 2011 Issued
Array ( [id] => 9781277 [patent_doc_number] => 08856498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Prefetch request circuit' [patent_app_type] => utility [patent_app_number] => 13/220006 [patent_app_country] => US [patent_app_date] => 2011-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8399 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13220006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/220006
Prefetch request circuit Aug 28, 2011 Issued
Array ( [id] => 7746843 [patent_doc_number] => 20120023311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'PROCESSOR APPARATUS AND MULTITHREAD PROCESSOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/215623 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 16237 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023311.pdf [firstpage_image] =>[orig_patent_app_number] => 13215623 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/215623
Processor apparatus and multithread processor apparatus Aug 22, 2011 Issued
Array ( [id] => 8059453 [patent_doc_number] => 20120079458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Debugging of a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 13/137208 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11130 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079458.pdf [firstpage_image] =>[orig_patent_app_number] => 13137208 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137208
Debugging of a data processing apparatus Jul 27, 2011 Issued
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