Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10556140 [patent_doc_number] => 09280342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Vector operations for compressing selected vector elements' [patent_app_type] => utility [patent_app_number] => 13/187132 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13187132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187132
Vector operations for compressing selected vector elements Jul 19, 2011 Issued
Array ( [id] => 9077440 [patent_doc_number] => 08555033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Extending operations of an application in a data processing system' [patent_app_type] => utility [patent_app_number] => 13/186556 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13186556 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/186556
Extending operations of an application in a data processing system Jul 19, 2011 Issued
Array ( [id] => 10078837 [patent_doc_number] => 09116685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Table call instruction for frequently called functions' [patent_app_type] => utility [patent_app_number] => 13/185644 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5373 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13185644 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185644
Table call instruction for frequently called functions Jul 18, 2011 Issued
Array ( [id] => 9961223 [patent_doc_number] => 09009447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-14 [patent_title] => 'Acceleration of string comparisons using vector instructions' [patent_app_type] => utility [patent_app_number] => 13/185244 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13185244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185244
Acceleration of string comparisons using vector instructions Jul 17, 2011 Issued
Array ( [id] => 9885918 [patent_doc_number] => 08972703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Multithreaded processor architecture with operational latency hiding' [patent_app_type] => utility [patent_app_number] => 13/180724 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 14715 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13180724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180724
Multithreaded processor architecture with operational latency hiding Jul 11, 2011 Issued
Array ( [id] => 7780598 [patent_doc_number] => 20120042154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Illegal mode change handling' [patent_app_type] => utility [patent_app_number] => 13/067808 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3711 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042154.pdf [firstpage_image] =>[orig_patent_app_number] => 13067808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067808
Illegal mode change handling Jun 27, 2011 Issued
Array ( [id] => 9077441 [patent_doc_number] => 08555032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Microcontroller programmable system on a chip with programmable interconnect' [patent_app_type] => utility [patent_app_number] => 13/169656 [patent_app_country] => US [patent_app_date] => 2011-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 36 [patent_no_of_words] => 18315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13169656 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/169656
Microcontroller programmable system on a chip with programmable interconnect Jun 26, 2011 Issued
Array ( [id] => 9954359 [patent_doc_number] => 09003171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Page fault prediction for processing vector instructions' [patent_app_type] => utility [patent_app_number] => 13/167630 [patent_app_country] => US [patent_app_date] => 2011-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 10690 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167630 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167630
Page fault prediction for processing vector instructions Jun 22, 2011 Issued
Array ( [id] => 10021234 [patent_doc_number] => 09063720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Instruction and logic for processing text strings' [patent_app_type] => utility [patent_app_number] => 13/164715 [patent_app_country] => US [patent_app_date] => 2011-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11694 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13164715 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/164715
Instruction and logic for processing text strings Jun 19, 2011 Issued
Array ( [id] => 9062813 [patent_doc_number] => 08549266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'System and method of instruction modification' [patent_app_type] => utility [patent_app_number] => 13/155291 [patent_app_country] => US [patent_app_date] => 2011-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13155291 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/155291
System and method of instruction modification Jun 6, 2011 Issued
Array ( [id] => 8407847 [patent_doc_number] => 20120239914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'MULTITHREADED PARALLEL EXECUTION DEVICE, BROADCAST STREAM PLAYBACK DEVICE, BROADCAST STREAM STORAGE DEVICE, STORED STREAM PLAYBACK DEVICE, STORED STREAM RE-ENCODING DEVICE, INTEGRATED CIRCUIT, MULTITHREADED PARALLEL EXECUTION METHOD, AND MULTITHREADED COMPILER' [patent_app_type] => utility [patent_app_number] => 13/319848 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13319848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/319848
Multithreaded parallel execution device, broadcast stream playback device, broadcast stream storage device, stored stream playback device, stored stream re-encoding device, integrated circuit, multithreaded parallel execution method, and multithreaded compiler Jun 2, 2011 Issued
Array ( [id] => 8222907 [patent_doc_number] => 20120137108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'SYSTEMS AND METHODS INTEGRATING BOOLEAN PROCESSING AND MEMORY' [patent_app_type] => utility [patent_app_number] => 13/114391 [patent_app_country] => US [patent_app_date] => 2011-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13114391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/114391
SYSTEMS AND METHODS INTEGRATING BOOLEAN PROCESSING AND MEMORY May 23, 2011 Abandoned
Array ( [id] => 9187060 [patent_doc_number] => 08627046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Data processing device' [patent_app_type] => utility [patent_app_number] => 13/113511 [patent_app_country] => US [patent_app_date] => 2011-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8210 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13113511 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/113511
Data processing device May 22, 2011 Issued
Array ( [id] => 9578810 [patent_doc_number] => 08769245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Very long instruction word (VLIW) processor with power management, and apparatus and method of power management therefor' [patent_app_type] => utility [patent_app_number] => 13/112307 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7958 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13112307 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/112307
Very long instruction word (VLIW) processor with power management, and apparatus and method of power management therefor May 19, 2011 Issued
Array ( [id] => 10901450 [patent_doc_number] => 08924693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Predicting a result for a predicate-generating instruction when processing vector instructions' [patent_app_type] => utility [patent_app_number] => 13/106775 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12955 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13106775 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/106775
Predicting a result for a predicate-generating instruction when processing vector instructions May 11, 2011 Issued
Array ( [id] => 10841191 [patent_doc_number] => 08868890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'No-delay microsequencer' [patent_app_type] => utility [patent_app_number] => 13/106119 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13106119 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/106119
No-delay microsequencer May 11, 2011 Issued
Array ( [id] => 8491399 [patent_doc_number] => 20120290806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'SELECTIVE ROUTING OF LOCAL MEMORY ACCESSES AND DEVICE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/103609 [patent_app_country] => US [patent_app_date] => 2011-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13103609 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/103609
Selective routing of local memory accesses and device thereof May 8, 2011 Issued
Array ( [id] => 9954355 [patent_doc_number] => 09003167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Data processing apparatus and data processing method' [patent_app_type] => utility [patent_app_number] => 13/102168 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 46 [patent_no_of_words] => 11875 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102168 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/102168
Data processing apparatus and data processing method May 5, 2011 Issued
Array ( [id] => 10841187 [patent_doc_number] => 08868886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Task switch immunized performance monitoring' [patent_app_type] => utility [patent_app_number] => 13/079189 [patent_app_country] => US [patent_app_date] => 2011-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3412 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13079189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/079189
Task switch immunized performance monitoring Apr 3, 2011 Issued
Array ( [id] => 8432720 [patent_doc_number] => 20120254596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'METHOD AND SYSTEM FOR CONTROLLING MESSAGE TRAFFIC BETWEEN TWO PROCESSORS' [patent_app_type] => utility [patent_app_number] => 13/077689 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5208 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13077689 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/077689
Method and system for controlling message traffic between two processors Mar 30, 2011 Issued
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