Eliseo Ramos Feliciano

Array ( [id] => 9967814 [patent_doc_number] => 09015449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Region-weighted accounting of multi-threaded processor core according to dispatch state' [patent_app_type] => utility [patent_app_number] => 13/072716 [patent_app_country] => US [patent_app_date] => 2011-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8260 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13072716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6104955 [patent_doc_number] => 20110167244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'EARLY INSTRUCTION TEXT BASED OPERAND STORE COMPARE REJECT AVOIDANCE' [patent_app_type] => utility [patent_app_number] => 13/050484 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3100 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20110167244.pdf [firstpage_image] =>[orig_patent_app_number] => 13050484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9680470 [patent_doc_number] => 08819397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Processor with increased efficiency via control word prediction' [patent_app_type] => utility [patent_app_number] => 13/037830 [patent_app_country] => US [patent_app_date] => 2011-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3352 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9652142 [patent_doc_number] => 08806176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Applying advanced energy manager in a distributed environment' [patent_app_type] => utility [patent_app_number] => 13/031915 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8544 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13031915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6189268 [patent_doc_number] => 20110125984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/012001 [patent_app_country] => US [patent_app_date] => 2011-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3996 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20110125984.pdf [firstpage_image] =>[orig_patent_app_number] => 13012001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9665817 [patent_doc_number] => 08812825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Methods and systems for managing performance and power utilization of a processor employing a fully multithreaded load threshold' [patent_app_type] => utility [patent_app_number] => 12/987591 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5022 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12987591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8280050 [patent_doc_number] => 20120173923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'ACCELERATING THE PERFORMANCE OF MATHEMATICAL FUNCTIONS IN HIGH PERFORMANCE COMPUTER SYSTEMS' [patent_app_type] => utility [patent_app_number] => 12/983092 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4214 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12983092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8279918 [patent_doc_number] => 20120173793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'MEMORY DEVICE USING EXTENDED INTERFACE COMMANDS' [patent_app_type] => utility [patent_app_number] => 12/982847 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9707325 [patent_doc_number] => 08832419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Enhanced microcode address stack pointer manipulation' [patent_app_type] => utility [patent_app_number] => 12/978471 [patent_app_country] => US [patent_app_date] => 2010-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12978471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9314905 [patent_doc_number] => 08656140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Data processing device' [patent_app_type] => utility [patent_app_number] => 12/963072 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6259 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8202042 [patent_doc_number] => 20120124589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'MATRIX ALGORITHM FOR SCHEDULING OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/945432 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8431 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124589.pdf [firstpage_image] =>[orig_patent_app_number] => 12945432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8558136 [patent_doc_number] => 08332621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Implementation of variable length instruction encoding using alias addressing' [patent_app_type] => utility [patent_app_number] => 12/900993 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4195 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12900993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8097811 [patent_doc_number] => 20120084511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'INEFFECTIVE PREFETCH DETERMINATION AND LATENCY OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/897008 [patent_app_country] => US [patent_app_date] => 2010-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084511.pdf [firstpage_image] =>[orig_patent_app_number] => 12897008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8045943 [patent_doc_number] => 20120072705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'Obtaining And Releasing Hardware Threads Without Hypervisor Involvement' [patent_app_type] => utility [patent_app_number] => 12/886091 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9089 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20120072705.pdf [firstpage_image] =>[orig_patent_app_number] => 12886091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9116161 [patent_doc_number] => 08572353 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-29 [patent_title] => 'Condensed router headers with low latency output port calculation' [patent_app_type] => utility [patent_app_number] => 12/886366 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 40948 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12886366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9629930 [patent_doc_number] => 08799624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-05 [patent_title] => 'Configurable device interfaces' [patent_app_type] => utility [patent_app_number] => 12/886382 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 40934 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12886382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8045951 [patent_doc_number] => 20120072707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'Scaleable Status Tracking Of Multiple Assist Hardware Threads' [patent_app_type] => utility [patent_app_number] => 12/886149 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20120072707.pdf [firstpage_image] =>[orig_patent_app_number] => 12886149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9326190 [patent_doc_number] => 08661227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Multi-level register file supporting multiple threads' [patent_app_type] => utility [patent_app_number] => 12/884411 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5774 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12884411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9326195 [patent_doc_number] => 08661232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Register state saving and restoring' [patent_app_type] => utility [patent_app_number] => 12/923357 [patent_app_country] => US [patent_app_date] => 2010-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10410 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12923357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9592812 [patent_doc_number] => 08782378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Dynamic instruction splitting' [patent_app_type] => utility [patent_app_number] => 12/923320 [patent_app_country] => US [patent_app_date] => 2010-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5583 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12923320 [rel_patent_id] =>[rel_patent_doc_number] =>)