Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7809017 [patent_doc_number] => 20120059971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOAD FORWARDING' [patent_app_type] => utility [patent_app_number] => 12/876912 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20120059971.pdf [firstpage_image] =>[orig_patent_app_number] => 12876912 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876912
METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOAD FORWARDING Sep 6, 2010 Abandoned
Array ( [id] => 9156751 [patent_doc_number] => 08589664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Program flow control' [patent_app_type] => utility [patent_app_number] => 12/923155 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5148 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12923155 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923155
Program flow control Sep 6, 2010 Issued
Array ( [id] => 6633986 [patent_doc_number] => 20100325396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'Multithread processor and register control method' [patent_app_type] => utility [patent_app_number] => 12/805630 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6180 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325396.pdf [firstpage_image] =>[orig_patent_app_number] => 12805630 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805630
Multithread processor and method of controlling multithread processor Aug 9, 2010 Issued
Array ( [id] => 8878743 [patent_doc_number] => 08473727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'History based pipelined branch prediction' [patent_app_type] => utility [patent_app_number] => 12/851906 [patent_app_country] => US [patent_app_date] => 2010-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4239 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12851906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/851906
History based pipelined branch prediction Aug 5, 2010 Issued
Array ( [id] => 7671515 [patent_doc_number] => 20110320784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE' [patent_app_type] => utility [patent_app_number] => 12/822553 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822553 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822553
VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE Jun 23, 2010 Abandoned
Array ( [id] => 8479183 [patent_doc_number] => 20120278589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'STORAGE SYSTEM COMPRISING MULTIPLE MICROPROCESSORS AND METHOD FOR SHARING PROCESSING IN THIS STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/919106 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 14120 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12919106 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/919106
Storage system comprising multiple microprocessors and method for sharing processing in this storage system Jun 16, 2010 Issued
Array ( [id] => 7521026 [patent_doc_number] => 07975134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Macroscalar processor architecture' [patent_app_type] => utility [patent_app_number] => 12/788250 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 41 [patent_no_of_words] => 25153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975134.pdf [firstpage_image] =>[orig_patent_app_number] => 12788250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/788250
Macroscalar processor architecture May 25, 2010 Issued
Array ( [id] => 9023441 [patent_doc_number] => 08533438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Store-to-load forwarding based on load/store address computation source information comparisons' [patent_app_type] => utility [patent_app_number] => 12/781274 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9183 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12781274 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781274
Store-to-load forwarding based on load/store address computation source information comparisons May 16, 2010 Issued
Array ( [id] => 9023440 [patent_doc_number] => 08533437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Guaranteed prefetch instruction' [patent_app_type] => utility [patent_app_number] => 12/781337 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4852 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12781337 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781337
Guaranteed prefetch instruction May 16, 2010 Issued
Array ( [id] => 6413662 [patent_doc_number] => 20100306516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'INFORMATION PROCESSING APPARATUS AND BRANCH PREDICTION METHOD' [patent_app_type] => utility [patent_app_number] => 12/780131 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10018 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306516.pdf [firstpage_image] =>[orig_patent_app_number] => 12780131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/780131
Information processing apparatus and branch prediction method May 13, 2010 Issued
Array ( [id] => 7588584 [patent_doc_number] => 20110283095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'Hardware Assist Thread for Increasing Code Parallelism' [patent_app_type] => utility [patent_app_number] => 12/778192 [patent_app_country] => US [patent_app_date] => 2010-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10183 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283095.pdf [firstpage_image] =>[orig_patent_app_number] => 12778192 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/778192
Hardware assist thread for increasing code parallelism May 11, 2010 Issued
Array ( [id] => 7588585 [patent_doc_number] => 20110283096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'REGISTER FILE SUPPORTING TRANSACTIONAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/778235 [patent_app_country] => US [patent_app_date] => 2010-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6194 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283096.pdf [firstpage_image] =>[orig_patent_app_number] => 12778235 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/778235
Register file supporting transactional processing May 11, 2010 Issued
Array ( [id] => 8229985 [patent_doc_number] => 20120144184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'DATA PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/390653 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 19286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13390653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/390653
Data processing device Apr 5, 2010 Issued
Array ( [id] => 4600642 [patent_doc_number] => 07984277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'System and method of instruction modification' [patent_app_type] => utility [patent_app_number] => 12/698809 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984277.pdf [firstpage_image] =>[orig_patent_app_number] => 12698809 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698809
System and method of instruction modification Feb 1, 2010 Issued
Array ( [id] => 6593374 [patent_doc_number] => 20100274972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'SYSTEMS, METHODS, AND APPARATUSES FOR PARALLEL COMPUTING' [patent_app_type] => utility [patent_app_number] => 12/646815 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 49178 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20100274972.pdf [firstpage_image] =>[orig_patent_app_number] => 12646815 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/646815
SYSTEMS, METHODS, AND APPARATUSES FOR PARALLEL COMPUTING Dec 22, 2009 Abandoned
Array ( [id] => 6628628 [patent_doc_number] => 20100100710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Information processing apparatus, cache memory controlling apparatus, and memory access order assuring method' [patent_app_type] => utility [patent_app_number] => 12/654380 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5823 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100710.pdf [firstpage_image] =>[orig_patent_app_number] => 12654380 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654380
Information processing apparatus, cache memory controlling apparatus, and memory access order assuring method Dec 16, 2009 Issued
Array ( [id] => 5976422 [patent_doc_number] => 20110153987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'REVERSE SIMULTANEOUS MULTI-THREADING' [patent_app_type] => utility [patent_app_number] => 12/640112 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6288 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20110153987.pdf [firstpage_image] =>[orig_patent_app_number] => 12640112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640112
Reverse simultaneous multi-threading Dec 16, 2009 Issued
Array ( [id] => 6337552 [patent_doc_number] => 20100199076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'COMPUTING APPARATUS AND METHOD OF HANDLING INTERRUPT' [patent_app_type] => utility [patent_app_number] => 12/639663 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3577 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199076.pdf [firstpage_image] =>[orig_patent_app_number] => 12639663 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639663
Computing apparatus and method of handling interrupt Dec 15, 2009 Issued
Array ( [id] => 8998090 [patent_doc_number] => 08521995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode' [patent_app_type] => utility [patent_app_number] => 12/638064 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11402 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12638064 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638064
Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode Dec 14, 2009 Issued
Array ( [id] => 6087979 [patent_doc_number] => 20110145543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'EXECUTION OF VARIABLE WIDTH VECTOR PROCESSING INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 12/638671 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145543.pdf [firstpage_image] =>[orig_patent_app_number] => 12638671 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638671
Execution of variable width vector processing instructions Dec 14, 2009 Issued
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