
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6087986
[patent_doc_number] => 20110145550
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[patent_kind] => A1
[patent_issue_date] => 2011-06-16
[patent_title] => 'NON-QUIESCING KEY SETTING FACILITY'
[patent_app_type] => utility
[patent_app_number] => 12/638314
[patent_app_country] => US
[patent_app_date] => 2009-12-15
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[pdf_file] => publications/A1/0145/20110145550.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/638314 | Non-quiescing key setting facility | Dec 14, 2009 | Issued |
Array
(
[id] => 6087992
[patent_doc_number] => 20110145553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-16
[patent_title] => 'ACCELERATING PARALLEL TRANSACTIONS USING CACHE RESIDENT TRANSACTIONS'
[patent_app_type] => utility
[patent_app_number] => 12/638214
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[patent_app_date] => 2009-12-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/638214 | Accelerating parallel transactions using cache resident transactions | Dec 14, 2009 | Issued |
Array
(
[id] => 6634057
[patent_doc_number] => 20100325400
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[patent_kind] => A1
[patent_issue_date] => 2010-12-23
[patent_title] => 'MICROPROCESSOR AND DATA WRITE-IN METHOD THEREOF'
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Array
(
[id] => 6584815
[patent_doc_number] => 20100235613
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[patent_kind] => A1
[patent_issue_date] => 2010-09-16
[patent_title] => 'METHOD, APPARATUS OR SOFTWARE FOR PROCESSING EXCEPTIONS PRODUCED BY AN APPLICATION PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 12/635783
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/635783 | Method, apparatus or software for processing exceptions produced by an application program | Dec 10, 2009 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/636218 | APPARATUS AND METHOD FOR DATA PROCESS | Dec 10, 2009 | Abandoned |
Array
(
[id] => 8878739
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[patent_issue_date] => 2013-06-25
[patent_title] => 'Computer program product for managing processing resources'
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Array
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[patent_app_number] => 12/634187
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Array
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[patent_title] => 'Reducing instruction collisions in a processor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/631098 | Reducing instruction collisions in a processor | Dec 3, 2009 | Issued |
Array
(
[id] => 4602836
[patent_doc_number] => 07979680
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/630775 | Multi-threaded parallel processor methods and apparatus | Dec 2, 2009 | Issued |
Array
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[id] => 7553160
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[patent_title] => 'Macroscalar processor architecture'
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[patent_app_number] => 12/614336
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/614336 | Macroscalar processor architecture | Nov 5, 2009 | Issued |
Array
(
[id] => 7521021
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[patent_title] => 'Selective hardware lock disabling'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/562457 | Selective hardware lock disabling | Sep 17, 2009 | Issued |
Array
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Array
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[id] => 6639855
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Array
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Array
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Array
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