Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6087986 [patent_doc_number] => 20110145550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'NON-QUIESCING KEY SETTING FACILITY' [patent_app_type] => utility [patent_app_number] => 12/638314 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16309 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145550.pdf [firstpage_image] =>[orig_patent_app_number] => 12638314 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638314
Non-quiescing key setting facility Dec 14, 2009 Issued
Array ( [id] => 6087992 [patent_doc_number] => 20110145553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'ACCELERATING PARALLEL TRANSACTIONS USING CACHE RESIDENT TRANSACTIONS' [patent_app_type] => utility [patent_app_number] => 12/638214 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145553.pdf [firstpage_image] =>[orig_patent_app_number] => 12638214 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638214
Accelerating parallel transactions using cache resident transactions Dec 14, 2009 Issued
Array ( [id] => 6634057 [patent_doc_number] => 20100325400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'MICROPROCESSOR AND DATA WRITE-IN METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/637305 [patent_app_country] => US [patent_app_date] => 2009-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5683 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325400.pdf [firstpage_image] =>[orig_patent_app_number] => 12637305 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/637305
MICROPROCESSOR AND DATA WRITE-IN METHOD THEREOF Dec 13, 2009 Abandoned
Array ( [id] => 6584815 [patent_doc_number] => 20100235613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'METHOD, APPARATUS OR SOFTWARE FOR PROCESSING EXCEPTIONS PRODUCED BY AN APPLICATION PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/635783 [patent_app_country] => US [patent_app_date] => 2009-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4527 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235613.pdf [firstpage_image] =>[orig_patent_app_number] => 12635783 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/635783
Method, apparatus or software for processing exceptions produced by an application program Dec 10, 2009 Issued
Array ( [id] => 6448596 [patent_doc_number] => 20100153688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'APPARATUS AND METHOD FOR DATA PROCESS' [patent_app_type] => utility [patent_app_number] => 12/636218 [patent_app_country] => US [patent_app_date] => 2009-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4827 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153688.pdf [firstpage_image] =>[orig_patent_app_number] => 12636218 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/636218
APPARATUS AND METHOD FOR DATA PROCESS Dec 10, 2009 Abandoned
Array ( [id] => 8878739 [patent_doc_number] => 08473723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Computer program product for managing processing resources' [patent_app_type] => utility [patent_app_number] => 12/635544 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12635544 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/635544
Computer program product for managing processing resources Dec 9, 2009 Issued
Array ( [id] => 8558133 [patent_doc_number] => 08332618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Out-of-order X86 microprocessor with fast shift-by-zero handling' [patent_app_type] => utility [patent_app_number] => 12/634187 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2906 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12634187 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/634187
Out-of-order X86 microprocessor with fast shift-by-zero handling Dec 8, 2009 Issued
Array ( [id] => 8998086 [patent_doc_number] => 08521991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Reducing instruction collisions in a processor' [patent_app_type] => utility [patent_app_number] => 12/631098 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5800 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12631098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631098
Reducing instruction collisions in a processor Dec 3, 2009 Issued
Array ( [id] => 4602836 [patent_doc_number] => 07979680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Multi-threaded parallel processor methods and apparatus' [patent_app_type] => utility [patent_app_number] => 12/630775 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7940 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979680.pdf [firstpage_image] =>[orig_patent_app_number] => 12630775 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630775
Multi-threaded parallel processor methods and apparatus Dec 2, 2009 Issued
Array ( [id] => 7553160 [patent_doc_number] => 08065502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Macroscalar processor architecture' [patent_app_type] => utility [patent_app_number] => 12/614336 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 95 [patent_no_of_words] => 38366 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065502.pdf [firstpage_image] =>[orig_patent_app_number] => 12614336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/614336
Macroscalar processor architecture Nov 5, 2009 Issued
Array ( [id] => 7521021 [patent_doc_number] => 07975129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Selective hardware lock disabling' [patent_app_type] => utility [patent_app_number] => 12/562457 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3163 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975129.pdf [firstpage_image] =>[orig_patent_app_number] => 12562457 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562457
Selective hardware lock disabling Sep 17, 2009 Issued
Array ( [id] => 6312545 [patent_doc_number] => 20100070739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'Multiprocessor system and control method thereof' [patent_app_type] => utility [patent_app_number] => 12/585620 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 12988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070739.pdf [firstpage_image] =>[orig_patent_app_number] => 12585620 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585620
Multiprocessor system and control method thereof Sep 17, 2009 Issued
Array ( [id] => 6639855 [patent_doc_number] => 20100005279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'Data processor' [patent_app_type] => utility [patent_app_number] => 12/585376 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 18122 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20100005279.pdf [firstpage_image] =>[orig_patent_app_number] => 12585376 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585376
Data processor Sep 13, 2009 Issued
Array ( [id] => 6217617 [patent_doc_number] => 20110138152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'INSTRUCTION CONTROL DEVICE' [patent_app_type] => utility [patent_app_number] => 13/059439 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11432 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138152.pdf [firstpage_image] =>[orig_patent_app_number] => 13059439 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/059439
INSTRUCTION CONTROL DEVICE Aug 17, 2009 Abandoned
Array ( [id] => 6564184 [patent_doc_number] => 20100017582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'STALL PREDICTION THREAD MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 12/542157 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017582.pdf [firstpage_image] =>[orig_patent_app_number] => 12542157 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/542157
Stall prediction thread management Aug 16, 2009 Issued
Array ( [id] => 8354995 [patent_doc_number] => 08250344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Methods and apparatus for dynamic prediction by software' [patent_app_type] => utility [patent_app_number] => 12/540522 [patent_app_country] => US [patent_app_date] => 2009-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4270 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12540522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/540522
Methods and apparatus for dynamic prediction by software Aug 12, 2009 Issued
Array ( [id] => 5459672 [patent_doc_number] => 20090259824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'RECONFIGURABLE INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/490608 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14236 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20090259824.pdf [firstpage_image] =>[orig_patent_app_number] => 12490608 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/490608
Reconfigurable integrated circuit Jun 23, 2009 Issued
Array ( [id] => 5369910 [patent_doc_number] => 20090307469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'REGISTER SET USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/477287 [patent_app_country] => US [patent_app_date] => 2009-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4811 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307469.pdf [firstpage_image] =>[orig_patent_app_number] => 12477287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/477287
Register set used in multithreaded parallel processor architecture Jun 2, 2009 Issued
Array ( [id] => 6117051 [patent_doc_number] => 20110191569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'DATA PROCESSING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 13/063347 [patent_app_country] => US [patent_app_date] => 2009-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 14856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20110191569.pdf [firstpage_image] =>[orig_patent_app_number] => 13063347 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/063347
Data processing device and semiconductor intergrated circuit device for a bi-endian system May 27, 2009 Issued
Array ( [id] => 5535270 [patent_doc_number] => 20090235058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'DATA PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/472193 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8161 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235058.pdf [firstpage_image] =>[orig_patent_app_number] => 12472193 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/472193
Data processing device May 25, 2009 Issued
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