
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5399961
[patent_doc_number] => 20090320024
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[patent_kind] => A1
[patent_issue_date] => 2009-12-24
[patent_title] => 'CONTROL DEVICE AND CONTROL METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/365290
[patent_app_country] => US
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Array
(
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[patent_doc_number] => 08745359
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[patent_kind] => B2
[patent_issue_date] => 2014-06-03
[patent_title] => 'Processor for concurrently executing plural instruction streams'
[patent_app_type] => utility
[patent_app_number] => 12/919448
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Array
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[patent_title] => 'Calculating an estimated time remaining for completion of a multi-phased and multi-threaded process'
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Array
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[patent_title] => 'Low burden system for allocating computational resources in a real time control environment'
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Array
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Array
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Array
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[patent_title] => 'SINGLE STEP MODE IN A SOFTWARE PIPELINE WITHIN A HIGHLY THREADED NETWORK ON A CHIP MICROPROCESSOR'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/358776 | Single step mode in a software pipeline within a highly threaded network on a chip microprocessor | Jan 22, 2009 | Issued |
Array
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[patent_title] => 'Multiprocessor system and method of synchronization for multiprocessor system'
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[patent_app_number] => 12/358233
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Array
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Array
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Array
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Array
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Array
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Array
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[patent_title] => 'METHOD AND APPARATUS FOR BINDING SHADOW REGISTERS TO VECTORED INTERRUPTS'
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Array
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| 12/318025 | Register renaming system | Dec 18, 2008 | Abandoned |
Array
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