Eliseo Ramos Feliciano

Array ( [id] => 18941738 [patent_doc_number] => 20240036877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => GENERATING AND EXECUTING A CONTROL FLOW [patent_app_type] => utility [patent_app_number] => 18/448079 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18810897 [patent_doc_number] => 20230385233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MULTIPLE ACCUMULATE BUSSES IN A SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/446357 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925553 [patent_doc_number] => 20240028557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => ISSUING INSTRUCTIONS ON A VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/365790 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18788146 [patent_doc_number] => 20230376563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => COMPUTATIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 18/230139 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19581267 [patent_doc_number] => 12147380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Computational memory with cooperation among rows of processing elements and memory thereof [patent_app_type] => utility [patent_app_number] => 18/224146 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11580 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18904643 [patent_doc_number] => 20240020128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Securing Conditional Speculative Instruction Execution [patent_app_type] => utility [patent_app_number] => 18/353558 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18755940 [patent_doc_number] => 20230359385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => QUICK CLEARING OF REGISTERS [patent_app_type] => utility [patent_app_number] => 18/353181 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19764604 [patent_doc_number] => 12222894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Compiler operations for tensor streaming processor [patent_app_type] => utility [patent_app_number] => 18/351916 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11899 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18741693 [patent_doc_number] => 20230350674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => INTERRUPTIBLE AND RESTARTABLE MATRIX MULTIPLICATION INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/220225 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19732873 [patent_doc_number] => 12210871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Model processing method and apparatus [patent_app_type] => utility [patent_app_number] => 18/344367 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 16521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18997706 [patent_doc_number] => 11914548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-27 [patent_title] => Flow model computation system with disconnected graphs [patent_app_type] => utility [patent_app_number] => 18/207432 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17035 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 546 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19514196 [patent_doc_number] => 20240345882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SYSTEMS AND METHODS FOR PROCESSING FUNCTIONS IN COMPUTATIONAL STORAGE [patent_app_type] => utility [patent_app_number] => 18/328693 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18904634 [patent_doc_number] => 20240020119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => VECTOR PROCESSOR WITH EXTENDED VECTOR REGISTERS [patent_app_type] => utility [patent_app_number] => 18/202928 [patent_app_country] => US [patent_app_date] => 2023-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18810725 [patent_doc_number] => 20230385061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => COMPUTING ACCELERATOR, DATA PROCESSOR AND ASSOCIATED METHOD [patent_app_type] => utility [patent_app_number] => 18/322416 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18810724 [patent_doc_number] => 20230385060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Determining Distances Between Vectors [patent_app_type] => utility [patent_app_number] => 18/199996 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18630403 [patent_doc_number] => 20230289296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/321050 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18677803 [patent_doc_number] => 20230315450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/313026 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19669815 [patent_doc_number] => 12182574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Technique for predicting behaviour of control flow instructions [patent_app_type] => utility [patent_app_number] => 18/312052 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 19274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19442949 [patent_doc_number] => 12093213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Computing efficient cross channel operations in parallel computing machines using systolic arrays [patent_app_type] => utility [patent_app_number] => 18/310129 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 24813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19653456 [patent_doc_number] => 12175248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Re-use of speculative load instruction results from wrong path [patent_app_type] => utility [patent_app_number] => 18/305151 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 16327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305151 [rel_patent_id] =>[rel_patent_doc_number] =>)