Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4830862 [patent_doc_number] => 20080127197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHOD AND SYSTEM FOR ON-DEMAND SCRATCH REGISTER RENAMING' [patent_app_type] => utility [patent_app_number] => 12/027665 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3466 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20080127197.pdf [firstpage_image] =>[orig_patent_app_number] => 12027665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/027665
METHOD AND SYSTEM FOR ON-DEMAND SCRATCH REGISTER RENAMING Feb 6, 2008 Abandoned
Array ( [id] => 5437782 [patent_doc_number] => 20090172369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SAVING AND RESTORING ARCHITECTURAL STATE FOR PROCESSOR CORES' [patent_app_type] => utility [patent_app_number] => 11/965167 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7002 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172369.pdf [firstpage_image] =>[orig_patent_app_number] => 11965167 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965167
Saving and restoring architectural state for processor cores Dec 26, 2007 Issued
Array ( [id] => 5437769 [patent_doc_number] => 20090172356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'COMPRESSED INSTRUCTION FORMAT' [patent_app_type] => utility [patent_app_number] => 11/965669 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6526 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172356.pdf [firstpage_image] =>[orig_patent_app_number] => 11965669 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965669
Compressed instruction format Dec 26, 2007 Issued
Array ( [id] => 5548140 [patent_doc_number] => 20090158017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'TARGET-FREQUENCY BASED INDIRECT JUMP PREDICTION FOR HIGH-PERFORMANCE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/957728 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158017.pdf [firstpage_image] =>[orig_patent_app_number] => 11957728 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957728
Target-frequency based indirect jump prediction for high-performance processors Dec 16, 2007 Issued
Array ( [id] => 4589836 [patent_doc_number] => 07831813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Uses of known good code for implementing processor architectural modifications' [patent_app_type] => utility [patent_app_number] => 11/957848 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831813.pdf [firstpage_image] =>[orig_patent_app_number] => 11957848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957848
Uses of known good code for implementing processor architectural modifications Dec 16, 2007 Issued
Array ( [id] => 5548133 [patent_doc_number] => 20090158010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Command Protocol for Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 11/955659 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4626 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158010.pdf [firstpage_image] =>[orig_patent_app_number] => 11955659 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955659
Command protocol for integrated circuits Dec 12, 2007 Issued
Array ( [id] => 4591963 [patent_doc_number] => 07836278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Three operand instruction extension for X86 architecture' [patent_app_type] => utility [patent_app_number] => 11/954623 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3692 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836278.pdf [firstpage_image] =>[orig_patent_app_number] => 11954623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954623
Three operand instruction extension for X86 architecture Dec 11, 2007 Issued
Array ( [id] => 4787666 [patent_doc_number] => 20080140995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Information processor and instruction fetch control method' [patent_app_type] => utility [patent_app_number] => 12/000164 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9047 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20080140995.pdf [firstpage_image] =>[orig_patent_app_number] => 12000164 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000164
Information processor and instruction fetch control method Dec 9, 2007 Issued
Array ( [id] => 5424191 [patent_doc_number] => 20090150647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'Processing Unit Incorporating Vectorizable Execution Unit' [patent_app_type] => utility [patent_app_number] => 11/952193 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10776 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150647.pdf [firstpage_image] =>[orig_patent_app_number] => 11952193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952193
Processing unit incorporating vectorizable execution unit Dec 6, 2007 Issued
Array ( [id] => 4641936 [patent_doc_number] => 08019970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Three-dimensional networking design structure' [patent_app_type] => utility [patent_app_number] => 11/946422 [patent_app_country] => US [patent_app_date] => 2007-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 2549 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019970.pdf [firstpage_image] =>[orig_patent_app_number] => 11946422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/946422
Three-dimensional networking design structure Nov 27, 2007 Issued
Array ( [id] => 28221 [patent_doc_number] => 07797512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Virtual core management' [patent_app_type] => utility [patent_app_number] => 11/933297 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 18779 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797512.pdf [firstpage_image] =>[orig_patent_app_number] => 11933297 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933297
Virtual core management Oct 30, 2007 Issued
Array ( [id] => 7972137 [patent_doc_number] => 07941647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination' [patent_app_type] => utility [patent_app_number] => 11/982419 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 61 [patent_no_of_words] => 88551 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941647.pdf [firstpage_image] =>[orig_patent_app_number] => 11982419 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/982419
Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination Oct 30, 2007 Issued
Array ( [id] => 4895276 [patent_doc_number] => 20080104376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Method and Apparatus for Performing Group Instructions' [patent_app_type] => utility [patent_app_number] => 11/842025 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 400 [patent_figures_cnt] => 400 [patent_no_of_words] => 81965 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104376.pdf [firstpage_image] =>[orig_patent_app_number] => 11842025 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842025
Method and Apparatus for Performing Group Instructions Oct 28, 2007 Abandoned
Array ( [id] => 5548135 [patent_doc_number] => 20090158012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Method and Apparatus for Performing Improved Group Instructions' [patent_app_type] => utility [patent_app_number] => 11/842038 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 403 [patent_figures_cnt] => 403 [patent_no_of_words] => 79400 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158012.pdf [firstpage_image] =>[orig_patent_app_number] => 11842038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842038
Method and apparatus for performing improved group instructions Oct 28, 2007 Issued
Array ( [id] => 4706338 [patent_doc_number] => 20080065862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Method and Apparatus for Performing Data Handling Operations' [patent_app_type] => utility [patent_app_number] => 11/842098 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 400 [patent_figures_cnt] => 400 [patent_no_of_words] => 81959 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065862.pdf [firstpage_image] =>[orig_patent_app_number] => 11842098 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842098
Method and Apparatus for Performing Data Handling Operations Oct 28, 2007 Abandoned
Array ( [id] => 4706336 [patent_doc_number] => 20080065860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Method and Apparatus for Performing Improved Data Handling Operations' [patent_app_type] => utility [patent_app_number] => 11/842119 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 400 [patent_figures_cnt] => 400 [patent_no_of_words] => 81961 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065860.pdf [firstpage_image] =>[orig_patent_app_number] => 11842119 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842119
Method and Apparatus for Performing Improved Data Handling Operations Oct 28, 2007 Abandoned
Array ( [id] => 4774105 [patent_doc_number] => 20080059767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Method and Apparatus for Performing Improved Group Floating-Point Operations' [patent_app_type] => utility [patent_app_number] => 11/842077 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 400 [patent_figures_cnt] => 400 [patent_no_of_words] => 81945 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059767.pdf [firstpage_image] =>[orig_patent_app_number] => 11842077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842077
Method and apparatus for performing improved group floating-point operations Oct 28, 2007 Issued
Array ( [id] => 4774104 [patent_doc_number] => 20080059766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Method and Apparatus for Improved Programmable Processor' [patent_app_type] => utility [patent_app_number] => 11/842006 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 397 [patent_figures_cnt] => 397 [patent_no_of_words] => 81954 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059766.pdf [firstpage_image] =>[orig_patent_app_number] => 11842006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842006
Method and Apparatus for Improved Programmable Processor Oct 28, 2007 Abandoned
Array ( [id] => 4653327 [patent_doc_number] => 20080040584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Method and Apparatus for Performing Group Floating-Point Operations' [patent_app_type] => utility [patent_app_number] => 11/842055 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 400 [patent_figures_cnt] => 400 [patent_no_of_words] => 79234 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040584.pdf [firstpage_image] =>[orig_patent_app_number] => 11842055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842055
Method and Apparatus for Performing Group Floating-Point Operations Oct 28, 2007 Abandoned
Array ( [id] => 4606359 [patent_doc_number] => 07987345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Performance monitors in a multithreaded processor architecture' [patent_app_type] => utility [patent_app_number] => 11/864368 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987345.pdf [firstpage_image] =>[orig_patent_app_number] => 11864368 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864368
Performance monitors in a multithreaded processor architecture Sep 27, 2007 Issued
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