
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 27296
[patent_doc_number] => 07802073
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-09-21
[patent_title] => 'Virtual core management'
[patent_app_type] => utility
[patent_app_number] => 11/781726
[patent_app_country] => US
[patent_app_date] => 2007-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
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[patent_no_of_words] => 18745
[patent_no_of_claims] => 18
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/802/07802073.pdf
[firstpage_image] =>[orig_patent_app_number] => 11781726
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/781726 | Virtual core management | Jul 22, 2007 | Issued |
Array
(
[id] => 4539890
[patent_doc_number] => 07953961
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-05-31
[patent_title] => 'Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder'
[patent_app_type] => utility
[patent_app_number] => 11/880863
[patent_app_country] => US
[patent_app_date] => 2007-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/953/07953961.pdf
[firstpage_image] =>[orig_patent_app_number] => 11880863
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/880863 | Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder | Jul 22, 2007 | Issued |
Array
(
[id] => 4653325
[patent_doc_number] => 20080040582
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'Data processing unit and data processing apparatus using data processing unit'
[patent_app_type] => utility
[patent_app_number] => 11/826598
[patent_app_country] => US
[patent_app_date] => 2007-07-17
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11826598
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/826598 | Data processing unit and data processing apparatus using data processing unit | Jul 16, 2007 | Issued |
Array
(
[id] => 107691
[patent_doc_number] => 07725680
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-05-25
[patent_title] => 'Pipeline interposer'
[patent_app_type] => utility
[patent_app_number] => 11/825203
[patent_app_country] => US
[patent_app_date] => 2007-07-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/725/07725680.pdf
[firstpage_image] =>[orig_patent_app_number] => 11825203
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/825203 | Pipeline interposer | Jul 4, 2007 | Issued |
Array
(
[id] => 5351465
[patent_doc_number] => 20090006826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'BRANCH PREDICTION METHODS AND DEVICES CAPABLE OF PREDICTING FIRST TAKEN BRANCH INSTRUCTION WITHIN PLURALITY OF FETCHED INSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 11/769712
[patent_app_country] => US
[patent_app_date] => 2007-06-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0006/20090006826.pdf
[firstpage_image] =>[orig_patent_app_number] => 11769712
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769712 | Branch prediction methods and devices capable of predicting first taken branch instruction within plurality of fetched instructions | Jun 27, 2007 | Issued |
Array
(
[id] => 4804738
[patent_doc_number] => 20080016327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'Register File Bypass With Optional Results Storage and Separate Predication Register File in a VLIW Processor'
[patent_app_type] => utility
[patent_app_number] => 11/769191
[patent_app_country] => US
[patent_app_date] => 2007-06-27
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[pdf_file] => publications/A1/0016/20080016327.pdf
[firstpage_image] =>[orig_patent_app_number] => 11769191
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769191 | Register file bypass with optional results storage and separate predication register file in a VLIW processor | Jun 26, 2007 | Issued |
Array
(
[id] => 37536
[patent_doc_number] => 07793079
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[patent_issue_date] => 2010-09-07
[patent_title] => 'Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction'
[patent_app_type] => utility
[patent_app_number] => 11/769132
[patent_app_country] => US
[patent_app_date] => 2007-06-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/793/07793079.pdf
[firstpage_image] =>[orig_patent_app_number] => 11769132
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769132 | Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction | Jun 26, 2007 | Issued |
Array
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[id] => 4804731
[patent_doc_number] => 20080016320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'Vector Predicates for Sub-Word Parallel Operations'
[patent_app_type] => utility
[patent_app_number] => 11/769198
[patent_app_country] => US
[patent_app_date] => 2007-06-27
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11769198
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769198 | Vector Predicates for Sub-Word Parallel Operations | Jun 26, 2007 | Abandoned |
Array
(
[id] => 5351457
[patent_doc_number] => 20090006818
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[patent_issue_date] => 2009-01-01
[patent_title] => 'Method and Apparatus for Multiple Load Instruction Execution'
[patent_app_type] => utility
[patent_app_number] => 11/769271
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769271 | Method and apparatus for multiple load instruction execution | Jun 26, 2007 | Issued |
Array
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[id] => 5351455
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[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'Inter-Cluster Communication Network And Heirarchical Register Files For Clustered VLIW Processors'
[patent_app_type] => utility
[patent_app_number] => 11/769212
[patent_app_country] => US
[patent_app_date] => 2007-06-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769212 | Inter-cluster communication network and heirarchical register files for clustered VLIW processors | Jun 26, 2007 | Issued |
Array
(
[id] => 58521
[patent_doc_number] => 07769987
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[patent_issue_date] => 2010-08-03
[patent_title] => 'Single hot forward interconnect scheme for delayed execution pipelines'
[patent_app_type] => utility
[patent_app_number] => 11/769104
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769104 | Single hot forward interconnect scheme for delayed execution pipelines | Jun 26, 2007 | Issued |
Array
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[id] => 5351447
[patent_doc_number] => 20090006808
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[patent_issue_date] => 2009-01-01
[patent_title] => 'ULTRASCALABLE PETAFLOP PARALLEL SUPERCOMPUTER'
[patent_app_type] => utility
[patent_app_number] => 11/768905
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[patent_app_date] => 2007-06-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/768905 | Ultrascalable petaflop parallel supercomputer | Jun 25, 2007 | Issued |
Array
(
[id] => 157804
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[patent_issue_date] => 2010-03-23
[patent_title] => 'Program subgraph identification'
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[firstpage_image] =>[orig_patent_app_number] => 11806907
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/806907 | Program subgraph identification | Jun 4, 2007 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/742905 | Method and apparatus for register renaming | Apr 30, 2007 | Issued |
Array
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[patent_title] => 'Universal branch identifier for invalidation of speculative instructions'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/787832 | Method of protecting a computer stack | Apr 17, 2007 | Issued |
Array
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