Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 27296 [patent_doc_number] => 07802073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-21 [patent_title] => 'Virtual core management' [patent_app_type] => utility [patent_app_number] => 11/781726 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 18745 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802073.pdf [firstpage_image] =>[orig_patent_app_number] => 11781726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781726
Virtual core management Jul 22, 2007 Issued
Array ( [id] => 4539890 [patent_doc_number] => 07953961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-31 [patent_title] => 'Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder' [patent_app_type] => utility [patent_app_number] => 11/880863 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 22061 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/953/07953961.pdf [firstpage_image] =>[orig_patent_app_number] => 11880863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/880863
Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder Jul 22, 2007 Issued
Array ( [id] => 4653325 [patent_doc_number] => 20080040582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Data processing unit and data processing apparatus using data processing unit' [patent_app_type] => utility [patent_app_number] => 11/826598 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6187 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040582.pdf [firstpage_image] =>[orig_patent_app_number] => 11826598 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/826598
Data processing unit and data processing apparatus using data processing unit Jul 16, 2007 Issued
Array ( [id] => 107691 [patent_doc_number] => 07725680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-25 [patent_title] => 'Pipeline interposer' [patent_app_type] => utility [patent_app_number] => 11/825203 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7640 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725680.pdf [firstpage_image] =>[orig_patent_app_number] => 11825203 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/825203
Pipeline interposer Jul 4, 2007 Issued
Array ( [id] => 5351465 [patent_doc_number] => 20090006826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'BRANCH PREDICTION METHODS AND DEVICES CAPABLE OF PREDICTING FIRST TAKEN BRANCH INSTRUCTION WITHIN PLURALITY OF FETCHED INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 11/769712 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006826.pdf [firstpage_image] =>[orig_patent_app_number] => 11769712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769712
Branch prediction methods and devices capable of predicting first taken branch instruction within plurality of fetched instructions Jun 27, 2007 Issued
Array ( [id] => 4804738 [patent_doc_number] => 20080016327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Register File Bypass With Optional Results Storage and Separate Predication Register File in a VLIW Processor' [patent_app_type] => utility [patent_app_number] => 11/769191 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10293 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016327.pdf [firstpage_image] =>[orig_patent_app_number] => 11769191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769191
Register file bypass with optional results storage and separate predication register file in a VLIW processor Jun 26, 2007 Issued
Array ( [id] => 37536 [patent_doc_number] => 07793079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction' [patent_app_type] => utility [patent_app_number] => 11/769132 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6180 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793079.pdf [firstpage_image] =>[orig_patent_app_number] => 11769132 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769132
Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction Jun 26, 2007 Issued
Array ( [id] => 4804731 [patent_doc_number] => 20080016320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Vector Predicates for Sub-Word Parallel Operations' [patent_app_type] => utility [patent_app_number] => 11/769198 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6278 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016320.pdf [firstpage_image] =>[orig_patent_app_number] => 11769198 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769198
Vector Predicates for Sub-Word Parallel Operations Jun 26, 2007 Abandoned
Array ( [id] => 5351457 [patent_doc_number] => 20090006818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Method and Apparatus for Multiple Load Instruction Execution' [patent_app_type] => utility [patent_app_number] => 11/769271 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8704 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006818.pdf [firstpage_image] =>[orig_patent_app_number] => 11769271 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769271
Method and apparatus for multiple load instruction execution Jun 26, 2007 Issued
Array ( [id] => 5351455 [patent_doc_number] => 20090006816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Inter-Cluster Communication Network And Heirarchical Register Files For Clustered VLIW Processors' [patent_app_type] => utility [patent_app_number] => 11/769212 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5910 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006816.pdf [firstpage_image] =>[orig_patent_app_number] => 11769212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769212
Inter-cluster communication network and heirarchical register files for clustered VLIW processors Jun 26, 2007 Issued
Array ( [id] => 58521 [patent_doc_number] => 07769987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Single hot forward interconnect scheme for delayed execution pipelines' [patent_app_type] => utility [patent_app_number] => 11/769104 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6764 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/769/07769987.pdf [firstpage_image] =>[orig_patent_app_number] => 11769104 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769104
Single hot forward interconnect scheme for delayed execution pipelines Jun 26, 2007 Issued
Array ( [id] => 5351447 [patent_doc_number] => 20090006808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'ULTRASCALABLE PETAFLOP PARALLEL SUPERCOMPUTER' [patent_app_type] => utility [patent_app_number] => 11/768905 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 37027 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11768905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768905
Ultrascalable petaflop parallel supercomputer Jun 25, 2007 Issued
Array ( [id] => 157804 [patent_doc_number] => 07685404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Program subgraph identification' [patent_app_type] => utility [patent_app_number] => 11/806907 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 9900 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685404.pdf [firstpage_image] =>[orig_patent_app_number] => 11806907 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/806907
Program subgraph identification Jun 4, 2007 Issued
Array ( [id] => 58520 [patent_doc_number] => 07769986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Method and apparatus for register renaming' [patent_app_type] => utility [patent_app_number] => 11/742905 [patent_app_country] => US [patent_app_date] => 2007-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7151 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/769/07769986.pdf [firstpage_image] =>[orig_patent_app_number] => 11742905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/742905
Method and apparatus for register renaming Apr 30, 2007 Issued
Array ( [id] => 4862205 [patent_doc_number] => 20080270774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Universal branch identifier for invalidation of speculative instructions' [patent_app_type] => utility [patent_app_number] => 11/799293 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5605 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270774.pdf [firstpage_image] =>[orig_patent_app_number] => 11799293 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/799293
Universal branch identifier for invalidation of speculative instructions Apr 29, 2007 Issued
Array ( [id] => 4862146 [patent_doc_number] => 20080270749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Instruction issue control within a multi-threaded in-order superscalar processor' [patent_app_type] => utility [patent_app_number] => 11/790483 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5251 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270749.pdf [firstpage_image] =>[orig_patent_app_number] => 11790483 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790483
Instruction issue control within a multi-threaded in-order superscalar processor Apr 24, 2007 Issued
Array ( [id] => 5226665 [patent_doc_number] => 20070255932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Data processor and data process method' [patent_app_type] => utility [patent_app_number] => 11/790156 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6212 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20070255932.pdf [firstpage_image] =>[orig_patent_app_number] => 11790156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790156
Data processor and data process method Apr 23, 2007 Issued
Array ( [id] => 146731 [patent_doc_number] => 07694106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Multiprocessor system' [patent_app_type] => utility [patent_app_number] => 11/785891 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8433 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694106.pdf [firstpage_image] =>[orig_patent_app_number] => 11785891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785891
Multiprocessor system Apr 19, 2007 Issued
Array ( [id] => 254446 [patent_doc_number] => 07581089 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-25 [patent_title] => 'Method of protecting a computer stack' [patent_app_type] => utility [patent_app_number] => 11/787832 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8812 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 513 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/581/07581089.pdf [firstpage_image] =>[orig_patent_app_number] => 11787832 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/787832
Method of protecting a computer stack Apr 17, 2007 Issued
Array ( [id] => 188414 [patent_doc_number] => 07650485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-19 [patent_title] => 'Structure and method for achieving very large lookahead instruction window via non-sequential instruction fetch and issue' [patent_app_type] => utility [patent_app_number] => 11/786337 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6594 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/650/07650485.pdf [firstpage_image] =>[orig_patent_app_number] => 11786337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/786337
Structure and method for achieving very large lookahead instruction window via non-sequential instruction fetch and issue Apr 9, 2007 Issued
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