Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 48715 [patent_doc_number] => 07779241 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-17 [patent_title] => 'History based pipelined branch prediction' [patent_app_type] => utility [patent_app_number] => 11/786336 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4189 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/779/07779241.pdf [firstpage_image] =>[orig_patent_app_number] => 11786336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/786336
History based pipelined branch prediction Apr 9, 2007 Issued
Array ( [id] => 4665438 [patent_doc_number] => 20080256345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System' [patent_app_type] => utility [patent_app_number] => 11/733589 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5808 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256345.pdf [firstpage_image] =>[orig_patent_app_number] => 11733589 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733589
Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system Apr 9, 2007 Issued
Array ( [id] => 7595782 [patent_doc_number] => 07620800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions' [patent_app_type] => utility [patent_app_number] => 11/733064 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 6602 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620800.pdf [firstpage_image] =>[orig_patent_app_number] => 11733064 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733064
Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions Apr 8, 2007 Issued
Array ( [id] => 4602839 [patent_doc_number] => 07979683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Multiple simultaneous context architecture' [patent_app_type] => utility [patent_app_number] => 11/696928 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979683.pdf [firstpage_image] =>[orig_patent_app_number] => 11696928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/696928
Multiple simultaneous context architecture Apr 4, 2007 Issued
Array ( [id] => 163321 [patent_doc_number] => 07676659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding' [patent_app_type] => utility [patent_app_number] => 11/696508 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676659.pdf [firstpage_image] =>[orig_patent_app_number] => 11696508 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/696508
System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding Apr 3, 2007 Issued
Array ( [id] => 4581438 [patent_doc_number] => 07840781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Circuit arrangement for profiling a programmable processor connected via a uni-directional bus' [patent_app_type] => utility [patent_app_number] => 11/732721 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3637 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840781.pdf [firstpage_image] =>[orig_patent_app_number] => 11732721 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732721
Circuit arrangement for profiling a programmable processor connected via a uni-directional bus Apr 3, 2007 Issued
Array ( [id] => 4722360 [patent_doc_number] => 20080244232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Pre-fetch apparatus' [patent_app_type] => utility [patent_app_number] => 11/731954 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4214 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244232.pdf [firstpage_image] =>[orig_patent_app_number] => 11731954 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/731954
Pre-fetch apparatus Apr 1, 2007 Issued
Array ( [id] => 220371 [patent_doc_number] => 07613905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Partial register forwarding for CPUs with unequal delay functional units' [patent_app_type] => utility [patent_app_number] => 11/695260 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5287 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613905.pdf [firstpage_image] =>[orig_patent_app_number] => 11695260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/695260
Partial register forwarding for CPUs with unequal delay functional units Apr 1, 2007 Issued
Array ( [id] => 4723123 [patent_doc_number] => 20080244570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'FACILITATING COMMUNICATION WITHIN AN EMULATED PROCESSING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 11/694155 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6215 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244570.pdf [firstpage_image] =>[orig_patent_app_number] => 11694155 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694155
Facilitating communication within an emulated processing environment Mar 29, 2007 Issued
Array ( [id] => 68925 [patent_doc_number] => 07761696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Quiescing and de-quiescing point-to-point links' [patent_app_type] => utility [patent_app_number] => 11/731746 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761696.pdf [firstpage_image] =>[orig_patent_app_number] => 11731746 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/731746
Quiescing and de-quiescing point-to-point links Mar 29, 2007 Issued
Array ( [id] => 5560213 [patent_doc_number] => 20090271790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'COMPUTER ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/293290 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 20209 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20090271790.pdf [firstpage_image] =>[orig_patent_app_number] => 12293290 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/293290
COMPUTER ARCHITECTURE Mar 18, 2007 Abandoned
Array ( [id] => 5024689 [patent_doc_number] => 20070150656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'CACHE FOR INSTRUCTION SET ARCHITECTURE USING INDEXES TO ACHIEVE COMPRESSION' [patent_app_type] => utility [patent_app_number] => 11/683026 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5720 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150656.pdf [firstpage_image] =>[orig_patent_app_number] => 11683026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683026
Cache for instruction set architecture using indexes to achieve compression Mar 6, 2007 Issued
Array ( [id] => 4808968 [patent_doc_number] => 20080172546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'DIGITAL SIGNAL PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/679028 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1796 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20080172546.pdf [firstpage_image] =>[orig_patent_app_number] => 11679028 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679028
Digital signal processor Feb 25, 2007 Issued
Array ( [id] => 188587 [patent_doc_number] => 07647484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Low-impact performance sampling within a massively parallel computer' [patent_app_type] => utility [patent_app_number] => 11/678208 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7155 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647484.pdf [firstpage_image] =>[orig_patent_app_number] => 11678208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678208
Low-impact performance sampling within a massively parallel computer Feb 22, 2007 Issued
Array ( [id] => 5161553 [patent_doc_number] => 20070174597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Multiple-thread processor with in-pipeline, thread selectable storage' [patent_app_type] => utility [patent_app_number] => 11/710112 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18288 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20070174597.pdf [firstpage_image] =>[orig_patent_app_number] => 11710112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/710112
Multiple-thread processor with in-pipeline, thread selectable storage Feb 22, 2007 Issued
Array ( [id] => 220374 [patent_doc_number] => 07613908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Selective hardware lock disabling' [patent_app_type] => utility [patent_app_number] => 11/710028 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3070 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613908.pdf [firstpage_image] =>[orig_patent_app_number] => 11710028 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/710028
Selective hardware lock disabling Feb 22, 2007 Issued
Array ( [id] => 4735519 [patent_doc_number] => 20080052501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Filtered Branch-prediction predicate generation' [patent_app_type] => utility [patent_app_number] => 11/709060 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16244 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052501.pdf [firstpage_image] =>[orig_patent_app_number] => 11709060 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709060
Filtered branch-prediction predicate generation Feb 21, 2007 Issued
Array ( [id] => 137215 [patent_doc_number] => 07698534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Reordering application code to improve processing performance' [patent_app_type] => utility [patent_app_number] => 11/708703 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3928 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698534.pdf [firstpage_image] =>[orig_patent_app_number] => 11708703 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708703
Reordering application code to improve processing performance Feb 20, 2007 Issued
Array ( [id] => 157809 [patent_doc_number] => 07685409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'On-demand multi-thread multimedia processor' [patent_app_type] => utility [patent_app_number] => 11/677362 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6214 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685409.pdf [firstpage_image] =>[orig_patent_app_number] => 11677362 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677362
On-demand multi-thread multimedia processor Feb 20, 2007 Issued
Array ( [id] => 188586 [patent_doc_number] => 07647483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Multi-threaded parallel processor methods and apparatus' [patent_app_type] => utility [patent_app_number] => 11/676837 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7890 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647483.pdf [firstpage_image] =>[orig_patent_app_number] => 11676837 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/676837
Multi-threaded parallel processor methods and apparatus Feb 19, 2007 Issued
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