Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4836591 [patent_doc_number] => 20080133888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Data processor' [patent_app_type] => utility [patent_app_number] => 11/707150 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17878 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133888.pdf [firstpage_image] =>[orig_patent_app_number] => 11707150 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707150
Data processor Feb 15, 2007 Issued
Array ( [id] => 1078865 [patent_doc_number] => 07617385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Method and apparatus for measuring pipeline stalls in a microprocessor' [patent_app_type] => utility [patent_app_number] => 11/675112 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9152 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/617/07617385.pdf [firstpage_image] =>[orig_patent_app_number] => 11675112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675112
Method and apparatus for measuring pipeline stalls in a microprocessor Feb 14, 2007 Issued
Array ( [id] => 7589676 [patent_doc_number] => 07664938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-16 [patent_title] => 'Semantic processor systems and methods' [patent_app_type] => utility [patent_app_number] => 11/675618 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 15070 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/664/07664938.pdf [firstpage_image] =>[orig_patent_app_number] => 11675618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675618
Semantic processor systems and methods Feb 14, 2007 Issued
Array ( [id] => 5298233 [patent_doc_number] => 20090013159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Queue Processor And Data Processing Method By The Queue Processor' [patent_app_type] => utility [patent_app_number] => 12/279288 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6065 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013159.pdf [firstpage_image] =>[orig_patent_app_number] => 12279288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/279288
Queue Processor And Data Processing Method By The Queue Processor Feb 8, 2007 Abandoned
Array ( [id] => 223454 [patent_doc_number] => 07610470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Preventing register data flow hazards in an SST processor' [patent_app_type] => utility [patent_app_number] => 11/703462 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5240 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/610/07610470.pdf [firstpage_image] =>[orig_patent_app_number] => 11703462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703462
Preventing register data flow hazards in an SST processor Feb 5, 2007 Issued
Array ( [id] => 4956509 [patent_doc_number] => 20080189533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Method, system and apparatus for generation of global branch history' [patent_app_type] => utility [patent_app_number] => 11/701720 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8119 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189533.pdf [firstpage_image] =>[orig_patent_app_number] => 11701720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701720
Method, system and apparatus for generation of global branch history Feb 1, 2007 Issued
Array ( [id] => 208477 [patent_doc_number] => 07631169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Fault recovery on a massively parallel computer system to handle node failures without ending an executing job' [patent_app_type] => utility [patent_app_number] => 11/670803 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3502 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/631/07631169.pdf [firstpage_image] =>[orig_patent_app_number] => 11670803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670803
Fault recovery on a massively parallel computer system to handle node failures without ending an executing job Feb 1, 2007 Issued
Array ( [id] => 241376 [patent_doc_number] => 07594101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Secure digital processing unit and method for protecting programs' [patent_app_type] => utility [patent_app_number] => 11/701954 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 3644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594101.pdf [firstpage_image] =>[orig_patent_app_number] => 11701954 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701954
Secure digital processing unit and method for protecting programs Feb 1, 2007 Issued
Array ( [id] => 329525 [patent_doc_number] => 07516328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Contents transmission/reception scheme with function for limiting recipients' [patent_app_type] => utility [patent_app_number] => 11/669727 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 14532 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516328.pdf [firstpage_image] =>[orig_patent_app_number] => 11669727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669727
Contents transmission/reception scheme with function for limiting recipients Jan 30, 2007 Issued
Array ( [id] => 265529 [patent_doc_number] => 07571303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Reconfigurable integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/669537 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 14220 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/571/07571303.pdf [firstpage_image] =>[orig_patent_app_number] => 11669537 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669537
Reconfigurable integrated circuit Jan 30, 2007 Issued
Array ( [id] => 1078864 [patent_doc_number] => 07617384 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-10 [patent_title] => 'Structured programming control flow using a disable mask in a SIMD architecture' [patent_app_type] => utility [patent_app_number] => 11/669513 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/617/07617384.pdf [firstpage_image] =>[orig_patent_app_number] => 11669513 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669513
Structured programming control flow using a disable mask in a SIMD architecture Jan 30, 2007 Issued
Array ( [id] => 5179378 [patent_doc_number] => 20070180438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Stall prediction thread management' [patent_app_type] => utility [patent_app_number] => 11/700448 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6620 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20070180438.pdf [firstpage_image] =>[orig_patent_app_number] => 11700448 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700448
Stall prediction thread management Jan 29, 2007 Issued
Array ( [id] => 362553 [patent_doc_number] => 07487332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method and apparatus for binding shadow registers to vectored interrupts' [patent_app_type] => utility [patent_app_number] => 11/668582 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5877 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487332.pdf [firstpage_image] =>[orig_patent_app_number] => 11668582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668582
Method and apparatus for binding shadow registers to vectored interrupts Jan 29, 2007 Issued
Array ( [id] => 7598107 [patent_doc_number] => 07584346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-01 [patent_title] => 'Method and apparatus for supporting different modes of multi-threaded speculative execution' [patent_app_type] => utility [patent_app_number] => 11/698479 [patent_app_country] => US [patent_app_date] => 2007-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7751 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/584/07584346.pdf [firstpage_image] =>[orig_patent_app_number] => 11698479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698479
Method and apparatus for supporting different modes of multi-threaded speculative execution Jan 24, 2007 Issued
Array ( [id] => 9629929 [patent_doc_number] => 08799623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Hierarchical reconfigurable computer architecture' [patent_app_type] => utility [patent_app_number] => 12/086971 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8169 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12086971 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/086971
Hierarchical reconfigurable computer architecture Dec 21, 2006 Issued
Array ( [id] => 8878736 [patent_doc_number] => 08473720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Method for providing data to a digital processing means' [patent_app_type] => utility [patent_app_number] => 12/097886 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 9897 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12097886 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/097886
Method for providing data to a digital processing means Dec 18, 2006 Issued
Array ( [id] => 4984536 [patent_doc_number] => 20070089095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'APPARATUS AND METHOD TO TRACE HIGH PERFORMANCE MULTI-ISSUE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/608725 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7770 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20070089095.pdf [firstpage_image] =>[orig_patent_app_number] => 11608725 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608725
APPARATUS AND METHOD TO TRACE HIGH PERFORMANCE MULTI-ISSUE PROCESSORS Dec 7, 2006 Abandoned
Array ( [id] => 823381 [patent_doc_number] => 07409529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Method and apparatus for a shift register based interconnection for a massively parallel processor array' [patent_app_type] => utility [patent_app_number] => 11/604907 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3188 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409529.pdf [firstpage_image] =>[orig_patent_app_number] => 11604907 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/604907
Method and apparatus for a shift register based interconnection for a massively parallel processor array Nov 27, 2006 Issued
Array ( [id] => 9130181 [patent_doc_number] => 08578137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Reducing aging effect on registers' [patent_app_type] => utility [patent_app_number] => 11/791145 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4802 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11791145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/791145
Reducing aging effect on registers Nov 2, 2006 Issued
Array ( [id] => 7598110 [patent_doc_number] => 07584343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Data reordering processor and method for use in an active memory device' [patent_app_type] => utility [patent_app_number] => 11/582650 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5808 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/584/07584343.pdf [firstpage_image] =>[orig_patent_app_number] => 11582650 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/582650
Data reordering processor and method for use in an active memory device Oct 16, 2006 Issued
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