Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5017643 [patent_doc_number] => 20070260852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'FETCH AND DISPATCH DISASSOCIATION APPARATUS FOR MULTI-STREAMING PROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/539322 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2082 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20070260852.pdf [firstpage_image] =>[orig_patent_app_number] => 11539322 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539322
Fetch and dispatch disassociation apparatus for multi-streaming processors Oct 5, 2006 Issued
Array ( [id] => 329490 [patent_doc_number] => 07516300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Active memory processing array topography and method' [patent_app_type] => utility [patent_app_number] => 11/544686 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4011 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516300.pdf [firstpage_image] =>[orig_patent_app_number] => 11544686 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/544686
Active memory processing array topography and method Oct 4, 2006 Issued
Array ( [id] => 599133 [patent_doc_number] => 07444496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Apparatus, system, and method for determining the consistency of a database' [patent_app_type] => utility [patent_app_number] => 11/535786 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10051 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444496.pdf [firstpage_image] =>[orig_patent_app_number] => 11535786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/535786
Apparatus, system, and method for determining the consistency of a database Sep 26, 2006 Issued
Array ( [id] => 10027648 [patent_doc_number] => 09069547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Instruction and logic for processing text strings' [patent_app_type] => utility [patent_app_number] => 11/525981 [patent_app_country] => US [patent_app_date] => 2006-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11669 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11525981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/525981
Instruction and logic for processing text strings Sep 21, 2006 Issued
Array ( [id] => 5195373 [patent_doc_number] => 20070083858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'RECONFIGURABLE SEMANTIC PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/469342 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9722 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083858.pdf [firstpage_image] =>[orig_patent_app_number] => 11469342 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469342
RECONFIGURABLE SEMANTIC PROCESSOR Aug 30, 2006 Abandoned
Array ( [id] => 4700214 [patent_doc_number] => 20080222398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Programmable processor with group floating-point operations' [patent_app_type] => utility [patent_app_number] => 11/511466 [patent_app_country] => US [patent_app_date] => 2006-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 149 [patent_figures_cnt] => 149 [patent_no_of_words] => 24151 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222398.pdf [firstpage_image] =>[orig_patent_app_number] => 11511466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/511466
Programmable processor with group floating-point operations Aug 28, 2006 Abandoned
Array ( [id] => 1078863 [patent_doc_number] => 07617383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Circular register arrays of a computer' [patent_app_type] => utility [patent_app_number] => 11/503372 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4163 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/617/07617383.pdf [firstpage_image] =>[orig_patent_app_number] => 11503372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/503372
Circular register arrays of a computer Aug 10, 2006 Issued
Array ( [id] => 4653330 [patent_doc_number] => 20080040587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Debug Circuit Comparing Processor Instruction Set Operating Mode' [patent_app_type] => utility [patent_app_number] => 11/463379 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3422 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040587.pdf [firstpage_image] =>[orig_patent_app_number] => 11463379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463379
Debug circuit comparing processor instruction set operating mode Aug 8, 2006 Issued
Array ( [id] => 297856 [patent_doc_number] => 07543135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Processor and method for selectively processing instruction to be read using instruction code already in pipeline or already stored in prefetch buffer' [patent_app_type] => utility [patent_app_number] => 11/497290 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3780 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543135.pdf [firstpage_image] =>[orig_patent_app_number] => 11497290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/497290
Processor and method for selectively processing instruction to be read using instruction code already in pipeline or already stored in prefetch buffer Aug 1, 2006 Issued
Array ( [id] => 4659551 [patent_doc_number] => 20080028413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'CONCURRENT PHYSICAL PROCESSOR REASSIGNMENT' [patent_app_type] => utility [patent_app_number] => 11/461153 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20080028413.pdf [firstpage_image] =>[orig_patent_app_number] => 11461153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461153
Concurrent physical processor reassignment method Jul 30, 2006 Issued
Array ( [id] => 208471 [patent_doc_number] => 07631168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-08 [patent_title] => 'Graphical interface for grouping concurrent computing units executing a concurrent computing process' [patent_app_type] => utility [patent_app_number] => 11/497871 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8551 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/631/07631168.pdf [firstpage_image] =>[orig_patent_app_number] => 11497871 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/497871
Graphical interface for grouping concurrent computing units executing a concurrent computing process Jul 30, 2006 Issued
Array ( [id] => 343153 [patent_doc_number] => 07502914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Transitive suppression of instruction replay' [patent_app_type] => utility [patent_app_number] => 11/496225 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7339 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502914.pdf [firstpage_image] =>[orig_patent_app_number] => 11496225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/496225
Transitive suppression of instruction replay Jul 30, 2006 Issued
Array ( [id] => 200871 [patent_doc_number] => 07640421 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method and system for determining context switch state' [patent_app_type] => utility [patent_app_number] => 11/460698 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640421.pdf [firstpage_image] =>[orig_patent_app_number] => 11460698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460698
Method and system for determining context switch state Jul 27, 2006 Issued
Array ( [id] => 885596 [patent_doc_number] => 07356671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-08 [patent_title] => 'SoC architecture for voice and video over data network applications' [patent_app_type] => utility [patent_app_number] => 11/460560 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4135 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/356/07356671.pdf [firstpage_image] =>[orig_patent_app_number] => 11460560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460560
SoC architecture for voice and video over data network applications Jul 26, 2006 Issued
Array ( [id] => 5516972 [patent_doc_number] => 20090217279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Method and Device for Controlling a Computer System' [patent_app_type] => utility [patent_app_number] => 11/988485 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3870 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217279.pdf [firstpage_image] =>[orig_patent_app_number] => 11988485 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/988485
Method and Device for Controlling a Computer System Jul 25, 2006 Abandoned
Array ( [id] => 156220 [patent_doc_number] => 07681022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Efficient interrupt return address save mechanism' [patent_app_type] => utility [patent_app_number] => 11/459695 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4016 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681022.pdf [firstpage_image] =>[orig_patent_app_number] => 11459695 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459695
Efficient interrupt return address save mechanism Jul 24, 2006 Issued
Array ( [id] => 5734391 [patent_doc_number] => 20060259508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'METHOD AND APPARATUS FOR DETECTING SEMANTIC ELEMENTS USING A PUSH DOWN AUTOMATON' [patent_app_type] => utility [patent_app_number] => 11/458544 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6411 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259508.pdf [firstpage_image] =>[orig_patent_app_number] => 11458544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458544
METHOD AND APPARATUS FOR DETECTING SEMANTIC ELEMENTS USING A PUSH DOWN AUTOMATON Jul 18, 2006 Abandoned
Array ( [id] => 10111333 [patent_doc_number] => 09146745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Method and apparatus for partitioned pipelined execution of multiple execution threads' [patent_app_type] => utility [patent_app_number] => 11/479245 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5614 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11479245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479245
Method and apparatus for partitioned pipelined execution of multiple execution threads Jun 28, 2006 Issued
Array ( [id] => 5927916 [patent_doc_number] => 20060242387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Processor, compiler and compilation method' [patent_app_type] => utility [patent_app_number] => 11/452282 [patent_app_country] => US [patent_app_date] => 2006-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15477 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242387.pdf [firstpage_image] =>[orig_patent_app_number] => 11452282 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/452282
Processor, compiler and compilation method Jun 13, 2006 Issued
Array ( [id] => 4572618 [patent_doc_number] => 07962720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Distributed processing system, distributed processing method and computer program' [patent_app_type] => utility [patent_app_number] => 11/922112 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 7234 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962720.pdf [firstpage_image] =>[orig_patent_app_number] => 11922112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/922112
Distributed processing system, distributed processing method and computer program May 31, 2006 Issued
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