Eliseo Ramos Feliciano

Array ( [id] => 128031 [patent_doc_number] => 07707394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Reducing the size of a data stream produced during instruction tracing' [patent_app_type] => utility [patent_app_number] => 11/442593 [patent_app_country] => US [patent_app_date] => 2006-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11403 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707394.pdf [firstpage_image] =>[orig_patent_app_number] => 11442593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7595780 [patent_doc_number] => 07620802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Instruction execution device, debugging method, debugging device, and debugging program' [patent_app_type] => utility [patent_app_number] => 11/440253 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 10204 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620802.pdf [firstpage_image] =>[orig_patent_app_number] => 11440253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5684360 [patent_doc_number] => 20060200630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'EMBEDDED SYSTEM WITH INSTRUCTION PREFETCHING DEVICE, AND METHOD FOR FETCHING INSTRUCTIONS IN EMBEDDED SYSTEMS' [patent_app_type] => utility [patent_app_number] => 11/419202 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3967 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200630.pdf [firstpage_image] =>[orig_patent_app_number] => 11419202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5627073 [patent_doc_number] => 20060265578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Detection of a sequencing error in the execution of a program' [patent_app_type] => utility [patent_app_number] => 11/437416 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3799 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265578.pdf [firstpage_image] =>[orig_patent_app_number] => 11437416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5627072 [patent_doc_number] => 20060265577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'REAL-TIME MONITORING, ALIGNMENT, AND TRANSLATION OF CPU STALLS OR EVENTS' [patent_app_type] => utility [patent_app_number] => 11/383361 [patent_app_country] => US [patent_app_date] => 2006-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5182 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265577.pdf [firstpage_image] =>[orig_patent_app_number] => 11383361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4448942 [patent_doc_number] => 07865694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Three-dimensional networking structure' [patent_app_type] => utility [patent_app_number] => 11/382967 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 1909 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865694.pdf [firstpage_image] =>[orig_patent_app_number] => 11382967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5892011 [patent_doc_number] => 20060277437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Command execution controlling apparatus, command execution instructing apparatus and command execution controlling method' [patent_app_type] => utility [patent_app_number] => 11/432107 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7541 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277437.pdf [firstpage_image] =>[orig_patent_app_number] => 11432107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 309481 [patent_doc_number] => 07533244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Network-on-chip dataflow architecture' [patent_app_type] => utility [patent_app_number] => 11/382382 [patent_app_country] => US [patent_app_date] => 2006-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4182 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533244.pdf [firstpage_image] =>[orig_patent_app_number] => 11382382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5663039 [patent_doc_number] => 20060253635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'METHOD AND APPARATUS FOR BINDING SHADOW REGISTERS TO VECTORED INTERRUPTS' [patent_app_type] => utility [patent_app_number] => 11/279914 [patent_app_country] => US [patent_app_date] => 2006-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5858 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253635.pdf [firstpage_image] =>[orig_patent_app_number] => 11279914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5121865 [patent_doc_number] => 20070143580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'METHODS AND APPARATUS FOR IMPROVING FETCHING AND DISPATCH OF INSTRUCTIONS IN MULTITHREADED PROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/278874 [patent_app_country] => US [patent_app_date] => 2006-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5900 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143580.pdf [firstpage_image] =>[orig_patent_app_number] => 11278874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 188585 [patent_doc_number] => 07647482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Methods and apparatus for dynamic register scratching' [patent_app_type] => utility [patent_app_number] => 11/395373 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3985 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647482.pdf [firstpage_image] =>[orig_patent_app_number] => 11395373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 265527 [patent_doc_number] => 07571301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors' [patent_app_type] => utility [patent_app_number] => 11/395841 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4882 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/571/07571301.pdf [firstpage_image] =>[orig_patent_app_number] => 11395841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 846198 [patent_doc_number] => 07389403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-17 [patent_title] => 'Adaptive computing ensemble microprocessor architecture' [patent_app_type] => utility [patent_app_number] => 11/277761 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 22910 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389403.pdf [firstpage_image] =>[orig_patent_app_number] => 11277761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5849815 [patent_doc_number] => 20060233006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Programmable pipeline array' [patent_app_type] => utility [patent_app_number] => 11/390181 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4030 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20060233006.pdf [firstpage_image] =>[orig_patent_app_number] => 11390181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 599141 [patent_doc_number] => 07444499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Method and system for trace generation using memory index hashing' [patent_app_type] => utility [patent_app_number] => 11/391116 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 15658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444499.pdf [firstpage_image] =>[orig_patent_app_number] => 11391116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 336718 [patent_doc_number] => 07509481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Patchable and/or programmable pre-decode' [patent_app_type] => utility [patent_app_number] => 11/277735 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7414 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509481.pdf [firstpage_image] =>[orig_patent_app_number] => 11277735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7690022 [patent_doc_number] => 20070234011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Method and system for on-demand scratch register renaming' [patent_app_type] => utility [patent_app_number] => 11/390785 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234011.pdf [firstpage_image] =>[orig_patent_app_number] => 11390785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5064821 [patent_doc_number] => 20070226463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'PATCHABLE AND/OR PROGRAMMABLE DECODE USING PREDECODE SELECTION' [patent_app_type] => utility [patent_app_number] => 11/277716 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7429 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226463.pdf [firstpage_image] =>[orig_patent_app_number] => 11277716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5161547 [patent_doc_number] => 20070174591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 11/277622 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7774 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20070174591.pdf [firstpage_image] =>[orig_patent_app_number] => 11277622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 237692 [patent_doc_number] => 07596681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Processor and processing method for reusing arbitrary sections of program code' [patent_app_type] => utility [patent_app_number] => 11/388846 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3544 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596681.pdf [firstpage_image] =>[orig_patent_app_number] => 11388846 [rel_patent_id] =>[rel_patent_doc_number] =>)